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hcs08 microcontrollers freescale.com mc9s08de60 MC9S08DE32 data sheet mc9s08de60 rev. 3 6/2008

8-bit hcs08 central processor unit (cpu) 40-mhz hcs08 cpu (20-mhz bus) hc08 instruction set with added bgnd instruction support for up to 32 interrupt/reset sources on-chip memory flash read/program/erase over full operating voltage and temperature; error correction code mc9s08de60 = 60k MC9S08DE32 = 32k up to 2k eeprom in-circuit programmable memory; 8-byte single-page or 4-byte dual-page erase sector; program and erase while executing flash; erase abort up to 4k random-access memory (ram) power-saving modes two very low-power stop modes reduced power wait mode very low-power real-time interrupt for use in run, wait, and stop clock source options oscillator (xosc) ?loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz multi-purpose clock generator (mcg) ?pll and fll modes (fll capable of 1.5% deviation using internal temperature compensation); internal reference clock with trim adjustment (trimmed at factory, with trim value stored in ?sh); external reference with oscillator/resonator options system protection watchdog computer operating properly (cop) reset with option to run from backup dedicated 1-khz internal clock source or bus clock low-voltage detection with reset or interrupt; selectable trip points illegal opcode detection with reset illegal address detection with reset flash block protect loss-of-lock protection development support single-wire background debug interface on-chip, in-circuit emulation (ice) with real-time bus capture peripherals adc ?24-channel, 12-bit resolution, 2.5 s conversion time, automatic compare function, temperature sensor, internal bandgap reference channel acmpx ?two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to ?ed internal bandgap reference voltage mscan can protocol - version 2.0 a, b; standard and extended data frames; support for remote frames; ve receive buffers with fifo storage scheme; ?xible identi?r acceptance ?ters programmable as: 2 x 32-bit, 4 x 16-bit, or 8 x 8-bit scix ?two scis supporting lin 2.0 protocol and sae j2602 protocols; full duplex non-return to zero (nrz); master extended break generation; slave extended break detection; wakeup on active edge spi ?full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-?st or lsb-?st shifting iic ?up to 100 kbps with maximum bus loading; multi-master operation; programmable slave address; general call address; interrupt driven byte-by-byte data transfer tpmx ?one 6-channel (tpm1) and one 2-channel (tpm2); selectable input capture, output compare, or buffered edge-aligned pwm on each channel rtc (real-time counter) 8-bit modulus counter with binary or decimal based prescaler; real-time clock capabilities using external crystal and rtc for precise time base, time-of-day, calendar or task scheduling functions; free running on-chip low power oscillator (1 khz) for cyclic wake-up without external components input/output 53 general-purpose input/output (i/o) pins and 1 input-only pin 24 interrupt pins with selectable polarity on each pin hysteresis and con?urable pull device on all input pins con?urable slew rate and drive strength on all output pins package 64-pin low-pro?e quad ?t-pack (lqfp) 10x10 mm mc9s08de60 series features

mc9s08de60 data sheet covers mc9s08de60 MC9S08DE32 mc9s08de60 rev. 3 6/2008 freescale and the freescale logo are trademarks of freescale semiconductor, inc. freescale semiconductor, inc., 2007-2008. all rights reserved.
mc9s08de60 series data sheet, rev. 3 6 freescale semiconductor revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. revision number revision date description of changes 1 6/2006 advance information version for alpha samples customers 2 9/2007 product launch. removed the 64-pin qfn package. changed from standard to extended mode for mscan registers in register summary. corrected block diagrams for sci. updated the latest temp sensor information. made ftstmod reserved. updated device to use the adc 12-bit module. revised the mcg module. updated the tpm block module to version 3. added the tpm block module version 2 as an appendix for devices using 3m05c (or earlier) mask sets. heavily revised the electricals appendix. 3 6/2008 sustaining update. incorporated ps issues # 2765, 3177, 3236, 3292, 3311, 3312, 3326, 3335, 3345, 3382, 2795, 3382 and 3386 pll jitter spec update. also, added internal reference clock trim adjustment statement to features page. updated the tpm module to the latest version. adjusted values in table a-13 control timing row 2 and in table a-6 dc characteristics row 24 so that it references 5.0 v instead of 3.0 v. freescale semiconductor, inc., 2007-2008. all rights reserved. this product incorporates superflash ? technology licensed from sst.
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 7 list of chapters chapter title page chapter 1 device overview .............................................................................. 21 chapter 2 pins and connections ..................................................................... 27 chapter 3 modes of operation ......................................................................... 33 chapter 4 memory ............................................................................................. 39 chapter 5 resets, interrupts, and general system control.......................... 69 chapter 6 parallel input/output control.......................................................... 85 chapter 7 central processor unit (s08cpuv3) ............................................ 115 chapter 8 multi-purpose clock generator (s08mcgv1) ............................. 135 chapter 9 analog comparator (s08acmpv3) .............................................. 167 chapter 10 analog-to-digital converter (s08adc12v1)................................ 173 chapter 11 inter-integrated circuit (s08iicv2) ............................................... 199 chapter 12 freescale controller area network (s08mscanv1) .................. 219 chapter 13 serial peripheral interface (s08spiv3) ........................................ 273 chapter 14 serial communications interface (s08sciv4)............................. 289 chapter 15 real-time counter (s08rtcv1) ................................................... 309 chapter 16 timer pulse-width modulator (s08tpmv3) ................................. 319 chapter 17 development support ................................................................... 347 appendix a electrical characteristics.............................................................. 369 appendix b timer pulse-width modulator (tpmv2) ....................................... 393 appendix c ordering information and mechanical drawings........................ 407

mc9s08de60 series data sheet, rev. 3 freescale semiconductor 9 contents section number title page chapter 1 device overview 1.1 devices in the mc9s08de60 series............................................................................................ ....21 1.2 mcu block diagram ........................................................................................................... ............22 1.3 system clock distribution ................................................................................................... ............24 chapter 2 pins and connections 2.1 device pin assignment ....................................................................................................... .............27 2.2 recommended system connections .............................................................................................. ..28 2.2.1 power ..................................................................................................................... ...........29 2.2.2 oscillator ................................................................................................................ ...........29 2.2.3 reset .......................................................................................................................... ....29 2.2.4 background / mode select (bkgd/ms) ..........................................................................30 2.2.5 adc reference pins (v refh , v refl ) ..............................................................................30 2.2.6 general-purpose i/o and peripheral ports ........................................................................30 chapter 3 modes of operation 3.1 introduction ................................................................................................................ ......................33 3.2 features .................................................................................................................... ........................33 3.3 run mode .................................................................................................................... .....................33 3.4 active background mode...................................................................................................... ...........33 3.5 wait mode ................................................................................................................... .....................34 3.6 stop modes.................................................................................................................. .....................35 3.6.1 stop3 mode ................................................................................................................ .......35 3.6.2 stop2 mode ................................................................................................................ .......36 3.6.3 on-chip peripheral modules in stop modes ....................................................................37 chapter 4 memory 4.1 mc9s08de60 series memory map ................................................................................................39 4.2 reset and interrupt vector assignments ...................................................................................... ....40 4.3 register addresses and bit assignments...................................................................................... ...41 4.4 ram......................................................................................................................... ........................49 4.5 flash and eeprom ............................................................................................................ .............49 4.5.1 features .................................................................................................................. ...........49
mc9s08de60 series data sheet, rev. 3 10 freescale semiconductor section number title page 4.5.2 program and erase times .................................................................................................50 4.5.3 program and erase command execution .........................................................................50 4.5.4 burst program execution ..................................................................................................52 4.5.5 sector erase abort ........................................................................................................ ....54 4.5.6 access errors ............................................................................................................. .......55 4.5.7 block protection .......................................................................................................... ......56 4.5.8 vector redirection ........................................................................................................ ....56 4.5.9 security .................................................................................................................. ...........56 4.5.10 error correction code .................................................................................................... ...58 4.5.11 eeprom mapping ...........................................................................................................58 4.5.12 flash and eeprom registers and control bits ...............................................................58 chapter 5 resets, interrupts, and general system control 5.1 introduction ................................................................................................................ ......................69 5.2 features .................................................................................................................... ........................69 5.3 mcu reset ................................................................................................................... ....................69 5.4 computer operating properly (cop) watchdog..............................................................................70 5.5 interrupts .................................................................................................................. ........................71 5.5.1 interrupt stack frame ..................................................................................................... ..72 5.5.2 external interrupt request (irq) pin ...............................................................................72 5.5.3 interrupt vectors, sources, and local masks ....................................................................73 5.6 low-voltage detect (lvd) system ............................................................................................. ....75 5.6.1 power-on reset operation ...............................................................................................75 5.6.2 low-voltage detection (lvd) reset operation ...............................................................75 5.6.3 low-voltage warning (lvw) interrupt operation ...........................................................75 5.7 mclk output ................................................................................................................. .................75 5.8 reset, interrupt, and system control registers and control bits ....................................................76 5.8.1 interrupt pin request status and control register (irqsc) ............................................77 5.8.2 system reset status register (srs) .................................................................................78 5.8.3 system background debug force reset register (sbdfr) ............................................79 5.8.4 system options register 1 (sopt1) ................................................................................80 5.8.5 system options register 2 (sopt2) ................................................................................81 5.8.6 system device identi?ation register (sdidh, sdidl) ................................................82 5.8.7 system power management status and control 1 register (spmsc1) ...........................83 5.8.8 system power management status and control 2 register (spmsc2) ...........................84 chapter 6 parallel input/output control 6.1 port data and data direction ................................................................................................ ...........85 6.2 pull-up, slew rate, and drive strength...................................................................................... ......86 6.3 pin interrupts .............................................................................................................. ......................87
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 11 section number title page 6.3.1 edge only sensitivity ..................................................................................................... ..87 6.3.2 edge and level sensitivity ................................................................................................88 6.3.3 pull-up/pull-down resistors .............................................................................................88 6.3.4 pin interrupt initialization .............................................................................................. ...88 6.4 pin behavior in stop modes.................................................................................................. ...........88 6.5 parallel i/o and pin control registers ...................................................................................... .......89 6.5.1 port a registers .......................................................................................................... ......90 6.5.2 port b registers .......................................................................................................... ......94 6.5.3 port c registers .......................................................................................................... ......98 6.5.4 port d registers .......................................................................................................... ....101 6.5.5 port e registers .......................................................................................................... .....105 6.5.6 port f registers .......................................................................................................... .....108 6.5.7 port g registers .......................................................................................................... ....111 chapter 7 central processor unit (s08cpuv3) 7.1 introduction ................................................................................................................ ....................115 7.1.1 features .................................................................................................................. .........115 7.2 programmers model and cpu registers ......................................................................................116 7.2.1 accumulator (a) ........................................................................................................... ..116 7.2.2 index register (h:x) ...................................................................................................... .116 7.2.3 stack pointer (sp) ........................................................................................................ ...117 7.2.4 program counter (pc) ....................................................................................................117 7.2.5 condition code register (ccr) .....................................................................................117 7.3 addressing modes............................................................................................................ ..............119 7.3.1 inherent addressing mode (inh) ...................................................................................119 7.3.2 relative addressing mode (rel) ...................................................................................119 7.3.3 immediate addressing mode (imm) ..............................................................................119 7.3.4 direct addressing mode (dir) ......................................................................................119 7.3.5 extended addressing mode (ext) ................................................................................120 7.3.6 indexed addressing mode ..............................................................................................120 7.4 special operations.......................................................................................................... ................121 7.4.1 reset sequence ............................................................................................................ ...121 7.4.2 interrupt sequence ........................................................................................................ ..121 7.4.3 wait mode operation ......................................................................................................122 7.4.4 stop mode operation ......................................................................................................122 7.4.5 bgnd instruction .......................................................................................................... .123 7.5 hcs08 instruction set summary ............................................................................................... ....124 chapter 8 multi-purpose clock generator (s08mcgv1) 8.1 introduction ................................................................................................................ ....................135
mc9s08de60 series data sheet, rev. 3 12 freescale semiconductor section number title page 8.1.1 features .................................................................................................................. .........137 8.1.2 modes of operation ........................................................................................................139 8.2 external signal description ................................................................................................. ..........139 8.3 register de?ition .......................................................................................................... ...............140 8.3.1 mcg control register 1 (mcgc1) ...............................................................................140 8.3.2 mcg control register 2 (mcgc2) ...............................................................................141 8.3.3 mcg trim register (mcgtrm) ...................................................................................142 8.3.4 mcg status and control register (mcgsc) .................................................................143 8.3.5 mcg control register 3 (mcgc3) ...............................................................................144 8.4 functional description ...................................................................................................... .............146 8.4.1 operational modes ......................................................................................................... .146 8.4.2 mode switching ............................................................................................................ ..150 8.4.3 bus frequency divider ...................................................................................................151 8.4.4 low power bit usage .....................................................................................................151 8.4.5 internal reference clock ................................................................................................151 8.4.6 external reference clock ...............................................................................................151 8.4.7 fixed frequency clock ...................................................................................................152 8.5 initialization / application information .................................................................................... .....152 8.5.1 mcg module initialization sequence ............................................................................152 8.5.2 mcg mode switching ....................................................................................................153 8.5.3 calibrating the internal reference clock (irc) .............................................................164 chapter 9 analog comparator (s08acmpv3) 9.1 introduction ................................................................................................................ ....................167 9.1.1 acmp con?uration information ..................................................................................167 9.1.2 features .................................................................................................................. .........169 9.1.3 modes of operation ........................................................................................................169 9.1.4 block diagram ............................................................................................................. ...170 9.2 external signal description ................................................................................................. ..........170 9.3 memory map/register de?ition ............................................................................................... ...171 9.3.1 acmpx status and control register (acmpxsc) .........................................................171 9.4 functional description ...................................................................................................... .............172 chapter 10 analog-to-digital converter (s08adc12v1) 10.1 introduction ............................................................................................................... .....................173 10.1.1 analog power and ground signal names ......................................................................173 10.1.2 channel assignments ......................................................................................................173 10.1.3 alternate clock .......................................................................................................... .....174 10.1.4 hardware trigger ......................................................................................................... ...174 10.1.5 temperature sensor ....................................................................................................... .175
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 13 section number title page 10.1.6 features ................................................................................................................. ..........177 10.1.7 adc module block diagram .........................................................................................177 10.2 external signal description ................................................................................................ ...........178 10.2.1 analog power (v ddad ) ..................................................................................................179 10.2.2 analog ground (v ssad ) .................................................................................................179 10.2.3 voltage reference high (v refh ) ...................................................................................179 10.2.4 voltage reference low (v refl ) .....................................................................................179 10.2.5 analog channel inputs (adx) ........................................................................................179 10.3 register de?ition ......................................................................................................... ................179 10.3.1 status and control register 1 (adcsc1) ......................................................................179 10.3.2 status and control register 2 (adcsc2) ......................................................................181 10.3.3 data result high register (adcrh) .............................................................................181 10.3.4 data result low register (adcrl) ..............................................................................182 10.3.5 compare value high register (adccvh) ....................................................................182 10.3.6 compare value low register (adccvl) .....................................................................183 10.3.7 con?uration register (adccfg) ................................................................................183 10.3.8 pin control 1 register (apctl1) ..................................................................................184 10.3.9 pin control 2 register (apctl2) ..................................................................................185 10.3.10pin control 3 register (apctl3) ..................................................................................186 10.4 functional description ..................................................................................................... ..............187 10.4.1 clock select and divide control ....................................................................................188 10.4.2 input select and pin control ...........................................................................................188 10.4.3 hardware trigger ......................................................................................................... ...188 10.4.4 conversion control ....................................................................................................... ..188 10.4.5 automatic compare function .........................................................................................191 10.4.6 mcu wait mode operation ............................................................................................191 10.4.7 mcu stop3 mode operation ..........................................................................................192 10.4.8 mcu stop2 mode operation ..........................................................................................192 10.5 initialization information ................................................................................................. ..............193 10.5.1 adc module initialization example .............................................................................193 10.6 application information .................................................................................................... .............195 10.6.1 external pins and routing ..............................................................................................195 10.6.2 sources of error ......................................................................................................... .....196 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introduction ............................................................................................................... .....................199 11.1.1 features ................................................................................................................. ..........201 11.1.2 modes of operation ....................................................................................................... .201 11.1.3 block diagram ............................................................................................................ ....202 11.2 external signal description ................................................................................................ ...........202 11.2.1 scl ?serial clock line ...............................................................................................202
mc9s08de60 series data sheet, rev. 3 14 freescale semiconductor section number title page 11.2.2 sda ?serial data line ................................................................................................202 11.3 register de?ition ......................................................................................................... ................202 11.3.1 iic address register (iica) ...........................................................................................203 11.3.2 iic frequency divider register (iicf) ...........................................................................203 11.3.3 iic control register (iicc1) ..........................................................................................206 11.3.4 iic status register (iics) ...............................................................................................207 11.3.5 iic data i/o register (iicd) ..........................................................................................208 11.3.6 iic control register 2 (iicc2) .......................................................................................208 11.4 functional description ..................................................................................................... ..............209 11.4.1 iic protocol ............................................................................................................. ........209 11.4.2 10-bit address ........................................................................................................... ......213 11.4.3 general call address ..................................................................................................... .214 11.5 resets ..................................................................................................................... ........................214 11.6 interrupts ................................................................................................................. .......................214 11.6.1 byte transfer interrupt .................................................................................................. ..214 11.6.2 address detect interrupt .................................................................................................214 11.6.3 arbitration lost interrupt ............................................................................................... .214 11.7 initialization/application information ..................................................................................... ......216 chapter 12 freescale controller area network (s08mscanv1) 12.1 introduction ............................................................................................................... .....................219 12.1.1 features ................................................................................................................. ..........221 12.1.2 modes of operation ....................................................................................................... .221 12.1.3 block diagram ............................................................................................................ ....222 12.2 external signal description ................................................................................................ ...........222 12.2.1 rxcan ?can receiver input pin .............................................................................222 12.2.2 txcan ?can transmitter output pin .....................................................................222 12.2.3 can system ............................................................................................................... ....222 12.3 register de?ition ......................................................................................................... ................223 12.3.1 mscan control register 0 (canctl0) ......................................................................223 12.3.2 mscan control register 1 (canctl1) ......................................................................226 12.3.3 mscan bus timing register 0 (canbtr0) ...............................................................227 12.3.4 mscan bus timing register 1 (canbtr1) ...............................................................228 12.3.5 mscan receiver interrupt enable register (canrier) .............................................231 12.3.6 mscan transmitter flag register (cantflg) ..........................................................232 12.3.7 mscan transmitter interrupt enable register (cantier) ........................................233 12.3.8 mscan transmitter message abort request register (cantarq) ...........................234 12.3.9 mscan transmitter message abort acknowledge register (cantaak) .................235 12.3.10mscan transmit buffer selection register (cantbsel) .........................................235 12.3.11mscan identi?r acceptance control register (canidac) ......................................236 12.3.12mscan miscellaneous register (canmisc) ..............................................................237
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 15 section number title page 12.3.13mscan receive error counter (canrxerr) ............................................................238 12.3.14mscan transmit error counter (cantxerr) ..........................................................239 12.3.15mscan identi?r acceptance registers (canidar0-7) ............................................239 12.3.16mscan identi?r mask registers (canidmr0?anidmr7) .................................240 12.4 programmers model of message storage .....................................................................................241 12.4.1 identi?r registers (idr0?dr3) ...................................................................................244 12.4.2 idr0?dr3 for standard identi?r mapping .................................................................246 12.4.3 data segment registers (dsr0-7) .................................................................................247 12.4.4 data length register (dlr) ...........................................................................................248 12.4.5 transmit buffer priority register (tbpr) ......................................................................249 12.4.6 time stamp register (tsrh?srl) .............................................................................249 12.5 functional description ..................................................................................................... ..............250 12.5.1 general .................................................................................................................. ..........250 12.5.2 message storage .......................................................................................................... ...251 12.5.3 identi?r acceptance filter .............................................................................................254 12.5.4 modes of operation ....................................................................................................... .261 12.5.5 low-power options ........................................................................................................262 12.5.6 reset initialization ..................................................................................................... .....268 12.5.7 interrupts ............................................................................................................... ..........268 12.6 initialization/application information ..................................................................................... ......270 12.6.1 mscan initialization .....................................................................................................270 12.6.2 bus-off recovery ......................................................................................................... ..271 chapter 13 serial peripheral interface (s08spiv3) 13.1 introduction ............................................................................................................... .....................273 13.1.1 features ................................................................................................................. ..........275 13.1.2 block diagrams ........................................................................................................... ...275 13.1.3 spi baud rate generation ..............................................................................................277 13.2 external signal description ................................................................................................ ...........278 13.2.1 spsck ?spi serial clock ............................................................................................278 13.2.2 mosi ?master data out, slave data in ......................................................................278 13.2.3 miso ?master data in, slave data out ......................................................................278 13.2.4 ss ?slave select ...........................................................................................................278 13.3 modes of operation......................................................................................................... ...............279 13.3.1 spi in stop modes ........................................................................................................ ..279 13.4 register de?ition ......................................................................................................... ................279 13.4.1 spi control register 1 (spic1) ......................................................................................279 13.4.2 spi control register 2 (spic2) ......................................................................................280 13.4.3 spi baud rate register (spibr) ....................................................................................281 13.4.4 spi status register (spis) ..............................................................................................282 13.4.5 spi data register (spid) ................................................................................................283
mc9s08de60 series data sheet, rev. 3 16 freescale semiconductor section number title page 13.5 functional description ..................................................................................................... ..............284 13.5.1 spi clock formats ........................................................................................................ ..284 13.5.2 spi interrupts ........................................................................................................... .......287 13.5.3 mode fault detection .....................................................................................................287 chapter 14 serial communications interface (s08sciv4) 14.1 introduction ............................................................................................................... .....................289 14.1.1 sci2 con?uration information .....................................................................................289 14.1.2 features ................................................................................................................. ..........291 14.1.3 modes of operation ....................................................................................................... .291 14.1.4 block diagram ............................................................................................................ ....292 14.2 register de?ition ......................................................................................................... ................294 14.2.1 sci baud rate registers (scixbdh, scixbdl) ..........................................................294 14.2.2 sci control register 1 (scixc1) ...................................................................................295 14.2.3 sci control register 2 (scixc2) ...................................................................................296 14.2.4 sci status register 1 (scixs1) ......................................................................................297 14.2.5 sci status register 2 (scixs2) ......................................................................................299 14.2.6 sci control register 3 (scixc3) ...................................................................................300 14.2.7 sci data register (scixd) .............................................................................................301 14.3 functional description ..................................................................................................... ..............301 14.3.1 baud rate generation .....................................................................................................301 14.3.2 transmitter functional description ................................................................................302 14.3.3 receiver functional description .....................................................................................303 14.3.4 interrupts and status flags ..............................................................................................305 14.3.5 additional sci functions ...............................................................................................306 chapter 15 real-time counter (s08rtcv1) 15.1 introduction ............................................................................................................... .....................309 15.1.1 rtc clock signal names ...............................................................................................309 15.1.2 features ................................................................................................................. ..........311 15.1.3 modes of operation ....................................................................................................... .311 15.1.4 block diagram ............................................................................................................ ....312 15.2 external signal description ................................................................................................ ...........312 15.3 register de?ition ......................................................................................................... ................312 15.3.1 rtc status and control register (rtcsc) ....................................................................313 15.3.2 rtc counter register (rtccnt) ..................................................................................314 15.3.3 rtc modulo register (rtcmod) ................................................................................314 15.4 functional description ..................................................................................................... ..............314 15.4.1 rtc operation example .................................................................................................315 15.5 initialization/application information ..................................................................................... ......316
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 17 section number title page chapter 16 timer pulse-width modulator (s08tpmv3) 16.1 introduction ............................................................................................................... .....................319 16.1.1 features ................................................................................................................. ..........321 16.1.2 modes of operation ....................................................................................................... .321 16.1.3 block diagram ............................................................................................................ ....322 16.2 signal description ......................................................................................................... .................324 16.2.1 detailed signal descriptions ...........................................................................................324 16.3 register de?ition ......................................................................................................... ................328 16.3.1 tpm status and control register (tpmxsc) ................................................................328 16.3.2 tpm-counter registers (tpmxcnth:tpmxcntl) ....................................................329 16.3.3 tpm counter modulo registers (tpmxmodh:tpmxmodl) ....................................330 16.3.4 tpm channel n status and control register (tpmxcnsc) ..........................................331 16.3.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) ..........................................332 16.4 functional description ..................................................................................................... ..............334 16.4.1 counter .................................................................................................................. ..........334 16.4.2 channel mode selection .................................................................................................336 16.5 reset overview ............................................................................................................. .................339 16.5.1 general .................................................................................................................. ..........339 16.5.2 description of reset operation .......................................................................................339 16.6 interrupts ................................................................................................................. .......................339 16.6.1 general .................................................................................................................. ..........339 16.6.2 description of interrupt operation ..................................................................................340 16.7 the differences from tpm v2 to tpm v3.....................................................................................341 chapter 17 development support 17.1 introduction ............................................................................................................... .....................347 17.1.1 forcing active background ............................................................................................347 17.1.2 features ................................................................................................................. ..........348 17.2 background debug controller (bdc) .......................................................................................... .348 17.2.1 bkgd pin description ...................................................................................................349 17.2.2 communication details ..................................................................................................350 17.2.3 bdc commands .............................................................................................................354 17.2.4 bdc hardware breakpoint .............................................................................................356 17.3 on-chip debug system (dbg) ................................................................................................. ....357 17.3.1 comparators a and b ......................................................................................................357 17.3.2 bus capture information and fifo operation ...............................................................357 17.3.3 change-of-flow information ..........................................................................................358 17.3.4 tag vs. force breakpoints and triggers .........................................................................358 17.3.5 trigger modes ............................................................................................................ .....359 17.3.6 hardware breakpoints ....................................................................................................361
mc9s08de60 series data sheet, rev. 3 18 freescale semiconductor section number title page 17.4 register de?ition ......................................................................................................... ................361 17.4.1 bdc registers and control bits .....................................................................................361 17.4.2 system background debug force reset register (sbdfr) ..........................................363 17.4.3 dbg registers and control bits .....................................................................................364 appendix a electrical characteristics a.1 introduction ................................................................................................................ ...................369 a.2 parameter classification .................................................................................................... ............369 a.3 absolute maximum ratings .................................................................................................... ......369 a.4 thermal characteristics ..................................................................................................... ............370 a.5 esd protection and latch-up immunity ......................................................................................372 a.6 dc characteristics .......................................................................................................... ...............373 a.7 supply current characteristics .............................................................................................. ........375 a.8 analog comparator (acmp) electricals ......................................................................................377 a.9 adc characteristics ......................................................................................................... .............377 a.10 external oscillator (xosc) characteristics .................................................................................381 a.11 mcg specifications ......................................................................................................... .............382 a.12 ac characteristics ......................................................................................................... ................384 a.12.1 control timing ........................................................................................................... ....384 a.12.2 timer/pwm ................................................................................................................ ....385 a.12.3 mscan .................................................................................................................... ......386 a.12.4 spi ...................................................................................................................... .............387 a.13 flash and eeprom ........................................................................................................... ...........390 a.14 emc performance ............................................................................................................ .............391 a.14.1 radiated emissions ....................................................................................................... ..391 appendix b timer pulse-width modulator (tpmv2) b.0.1 features .................................................................................................................. .........393 b.0.2 block diagram ............................................................................................................. ...393 b.1 external signal description ................................................................................................. ..........395 b.1.1 external tpm clock sources ..........................................................................................395 b.1.2 tpmxchn ?tpmx channel n i/o pins .......................................................................395 b.2 register de?ition .......................................................................................................... ...............395 b.2.1 timer status and control register (tpmxsc) ...............................................................396 b.2.2 timer counter registers (tpmxcnth:tpmxcntl) ...................................................397 b.2.3 timer counter modulo registers (tpmxmodh:tpmxmodl) ..................................398 b.2.4 timer channel n status and control register (tpmxcnsc) .........................................399 b.2.5 timer channel value registers (tpmxcnvh:tpmxcnvl) .........................................400 b.3 functional description ...................................................................................................... .............401 b.3.1 counter ................................................................................................................... .........401
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 19 section number title page b.3.2 channel mode selection .................................................................................................402 b.3.3 center-aligned pwm mode ...........................................................................................404 b.4 tpm interrupts .............................................................................................................. .................405 b.4.1 clearing timer interrupt flags .......................................................................................405 b.4.2 timer over?w interrupt description ............................................................................405 b.4.3 channel event interrupt description ..............................................................................406 b.4.4 pwm end-of-duty-cycle events ...................................................................................406 appendix c ordering information and mechanical drawings c.1 ordering information ........................................................................................................ ............407 c.1.1 mc9s08de60 series devices ........................................................................................407 c.2 mechanical drawings ......................................................................................................... ...........407

mc9s08de60 series data sheet, rev. 3 freescale semiconductor 21 chapter 1 device overview controller area network mc9s08de60 series devices are primarily focused at safety based applications. the error code correction (ecc) based flash provides the highest level of flash quality for the automotive safety markets. 1.1 devices in the mc9s08de60 series this data sheet covers members of the mc9s08de60 series of mcus: mc9s08de60 MC9S08DE32 table 1-1 summarizes the feature set available in the mc9s08de60 series. table 1-1. mc9s08de60 series features by mcu and pin count feature mc9s08de60 MC9S08DE32 flash size (bytes) ecc off ecc on 60032 44032 33792 22528 ram size (bytes) 4096 2048 eeprom size (bytes) 2048 1024 pin quantity 64 acmp1 yes acmp2 yes adc channels 24 dbg yes iic yes irq yes mcg yes mscan yes rtc yes sci1 yes sci2 yes spi yes tpm1 channels 6 tpm2 channels 2 xosc yes cop watchdog yes
chapter 1 device overview mc9s08de60 series data sheet, rev. 3 22 freescale semiconductor 1.2 mcu block diagram figure 1-1 is the mc9s08de60 series system-level block diagram.
chapter 1 device overview mc9s08de60 series data sheet, rev. 3 freescale semiconductor 23 figure 1-1. mc9s08de60/32 block diagram analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k / 44k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k / 22.5 k (ecc off / ecc on)
chapter 1 device overview mc9s08de60 series data sheet, rev. 3 24 freescale semiconductor table 1-2 provides the functional version of the on-chip modules. 1.3 system clock distribution figure 1-2 shows a simpli?d clock connection diagram. some modules in the mcu have selectable clock inputs as shown. the clock inputs to the modules indicate the clock(s) that are used to drive the module function. the following are the clocks used in this mcu: busclk ?the frequency of the bus is always half of mcgout. lpo independent 1-khz clock that can be selected as the source for the cop and rtc modules. mcgout ?primary output of the mcg and is twice the bus frequency. mcglclk development tools can select this clock source to speed up bdc communications in systems where busclk is con?ured to run at a very slow frequency. mcgerclk external reference clock can be selected as the rtc clock source. it can also be used as the alternate clock for the adc and mscan. mcgirclk ?internal reference clock can be selected as the rtc clock source. mcgffclk ?fixed frequency clock can be selected as clock source for the tpm1 and tpm2. tpm1clk ?external input clock source for tpm1. tpm2clk ?external input clock source for tpm2. table 1-2. module versions module version central processor unit (cpu) 3 multi-purpose clock generator (mcg) 1 analog comparator (acmp) 3 analog-to-digital converter (adc) 1 inter-integrated circuit (iic) 2 freescales can (mscan) 1 serial peripheral interface (spi) 3 serial communications interface (sci) 4 real-time counter (rtc) 1 timer pulse width modulator (tpm) 3 1 1 3m05c and older masks have tpm version 2. debug module (dbg) 2
chapter 1 device overview mc9s08de60 series data sheet, rev. 3 freescale semiconductor 25 figure 1-2. mc9s08de60/32 system clock distribution diagram tpm1 tpm2 iic sci1 sci2 bdc cpu adc mscan flash mcg mcgout 2 busclk mcglclk mcgerclk cop * the ?ed frequency clock (ffclk) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency. flash and eeprom have frequency requirements for program and erase operation. see the electricals appendix for details. adc has min and max frequency requirements. see the adc chapter and electricals appendix for details. xosc extal xtal eeprom spi ffclk* mcgffclk rtc 1 khz lpo tpm1clk tpm2clk mcgirclk 2
chapter 1 device overview mc9s08de60 series data sheet, rev. 3 26 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 27 chapter 2 pins and connections this section describes signals that connect to package pins. it includes pinout diagrams, recommended system connections, and detailed discussions of signals. 2.1 device pin assignment this section shows the pin assignments for mc9s08de60 series mcus in the available packages. figure 2-1. 64-pin lqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64-pin lqfp ptb1/pib1/adp9 ptb6/pib6/adp14 pta6/pia6/adp6 pte2/ ss ptc2/adp18 ptc5/adp21 pta0/pia0/adp0/mclk pta7/pia7/adp7/irq ptc1/adp17 ptc6/adp22 ptb0/pib0/adp8 ptb7/pib7/adp15 ptc0/adp16 ptc7/adp23 bkgd/ms v dd ptd7/pid7/tpm1ch5 v ss ptd6/pid6/tpm1ch4 ptg0/extal v dd ptg1/xtal v ss reset ptf7 ptf4/acmp2+ ptd5/pid5/tpm1ch3 ptf5/acmp2- ptd4/pid4/tpm1ch2 ptf6/acmp2o ptd3/pid3/tpm1ch1 pte0/txd1 ptd2/pid2/tpm1ch0 pte1/rxd1 ptb5/pib5/adp13 pte3/spsck pta5/pia5/adp5 pte4/scl/mosi ptc4/adp20 pte5/sda/miso ptb4/pib4/adp12 ptg2 pta4/pia4/adp4 ptg3 v dda ptf0/txd2 v refh ptf1/rxd2 v refl ptf2/tpm1clk/scl v ssa ptf3/tpm2clk/sda pta3/pia3/adp3/acmp1o ptg4 ptb3/pib3/adp11 ptg5 ptc3/adp19 pte6/txd2/txcan pta2/pia2/adp2/acmp1- pte7/rxd2/rxcan ptb2/pib2/adp10 ptd0/pid0/tpm2ch0 pta1/pia1/adp1/acmp1+ ptd1/pid1/tpm2ch1
chapter 2 pins and connections mc9s08de60 series data sheet, rev. 3 28 freescale semiconductor 2.2 recommended system connections figure 2-2 shows pin connections that are common to mc9s08de60 series application systems. figure 2-2. basic system connections notes: 1. external crystal circuit not required if using the internal clock option. 2. reset pin can only be used to reset into user mode, you can not enter bdm using reset pin. bdm can be entered by holding ms low during por or writing a 1 to bdfr in sbdfr with ms low after issuing bdm command. 3. rc filter on reset pin recommended for noisy environments. 4. for 32-pin and 48-pin packages: v dda and v ssa are double bonded to v refh and v refl respectively. port a c2 c1 x1 r f r s pta0/pia0/adp0/mclk pta1/pia1/adp1/acmp1+ pta2/pia2/adp2/acmp1- pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta6/pia6/adp6 pta7/pia7/adp7/irq port b ptb0/pib0/adp8 ptb1/pib1/adp9 port c port d ptd2/pid2/tpm1ch0 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 port e port g ptg2 ptg3 ptg4 ptg5 port f irq ptg0/extal ptg1/xtal ptf0/txd2 ptf1/rxd2 ptf2/tpm1clk/scl ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2 ptf6/acmp2o ptf7 pte0/txd1 pte1/rxd1 pte2/ ss pte3/spsck pte4/scl/mosi pte5/sda/miso pte6/txd2/txcan pte7/rxd2/rxcan ptd0/pid0/tpm2ch0 ptd1/pid1/tpm2ch1 ptb2/pib2/adp10 ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb6/pib6/adp14 ptb7/pib7/adp15 ptc0/adp16 ptc1/adp17 ptc2/adp18 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc6/adp22 ptc7/adp23 ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 c by 0.1 f v refh v refl v ssa v dda v dd v ss c by 0.1 f c blk 10 f + 5 v + system power bkgd/ms reset optional manual reset v dd background header 0.1 f v dd 4.7 k ?0 k
chapter 2 pins and connections mc9s08de60 series data sheet, rev. 3 freescale semiconductor 29 2.2.1 power v dd and v ss are the primary power supply pins for the mcu. this voltage source supplies power to all i/o buffer circuitry and to an internal voltage regulator. the internal voltage regulator provides regulated lower-voltage source to the cpu and other internal circuitry of the mcu. typically, application systems have two separate capacitors across the power pins. in this case, there should be a bulk electrolytic capacitor, such as a 10- f tantalum capacitor, to provide bulk charge storage for the overall system and a 0.1- f ceramic bypass capacitor located as near to the mcu power pins as practical to suppress high-frequency noise. the mc9s08de60 series has two v dd pins. each pin must have a bypass capacitor for best noise suppression. v dda and v ssa are the analog power supply pins for the mcu. this voltage source supplies power to the adc module. a 0.1- f ceramic bypass capacitor should be located as near to the mcu power pins as practical to suppress high-frequency noise. 2.2.2 oscillator immediately after reset, the mcu uses an internally generated clock provided by the multi-purpose clock generator (mcg) module. for more information on the mcg, see chapter 8, ?ulti-purpose clock generator (s08mcgv1). the oscillator (xosc) in this mcu is a pierce oscillator that can accommodate a crystal or ceramic resonator. rather than a crystal or ceramic resonator, an external oscillator can be connected to the extal input pin. refer to figure 2-2 for the following discussion. r s (when used) and r f should be low-inductance resistors such as carbon composition resistors. wire-wound resistors and some metal ?m resistors have too much inductance. c1 and c2 normally should be high-quality ceramic capacitors that are speci?ally designed for high-frequency applications. r f is used to provide a bias path to keep the extal input in its linear range during crystal startup; its value is not generally critical. typical systems use 1 m to 10 m . higher values are sensitive to humidity, and lower values reduce gain and (in extreme cases) could prevent startup. c1 and c2 are typically in the 5-pf to 25-pf range and are chosen to match the requirements of a speci? crystal or resonator. be sure to take into account printed circuit board (pcb) capacitance and mcu pin capacitance when selecting c1 and c2. the crystal manufacturer typically speci?s a load capacitance which is the series combination of c1 and c2 (which are usually the same size). as a ?st-order approximation, use 10 pf as an estimate of combined pin and pcb capacitance for each oscillator pin (extal and xtal). 2.2.3 reset reset is a dedicated pin with a pull-up device built in. it has input hysteresis, a high current output driver, and no output slew rate control. internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. this pin is normally connected to the standard 6-pin background debug connector so a development system can directly reset the mcu system. if desired, a manual external reset can be added by supplying a simple switch to ground (pull reset pin low to force a reset).
chapter 2 pins and connections mc9s08de60 series data sheet, rev. 3 30 freescale semiconductor whenever any reset is initiated (whether from an external signal or from an internal system), the reset pin is driven low for about 34 bus cycles. the reset circuitry decodes the cause of reset and records it by setting a corresponding bit in the system reset status register (srs). 2.2.4 background / mode select (bkgd/ms) while in reset, the bkgd/ms pin functions as a mode select pin. immediately after reset rises, the pin functions as the background pin and can be used for background debug communication. while functioning as a background or mode select pin, the pin includes an internal pull-up device, input hysteresis, a standard output driver, and no output slew rate control. if nothing is connected to this pin, the mcu will enter normal operating mode at the rising edge of reset. if a debug system is connected to the 6-pin standard background debug header, it can hold bkgd low during the rising edge of reset which forces the mcu to active background mode. the bkgd/ms pin is used primarily for background debug controller (bdc) communications using a custom protocol that uses 16 clock cycles of the target mcus bdc clock per bit time. the target mcus bdc clock could be as fast as the bus clock rate, so there should never be any signi?ant capacitance connected to the bkgd/ms pin that could interfere with background serial communications. although the bkgd/ms pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. small capacitances from cables and the absolute value of the internal pull-up device play almost no role in determining rise and fall times on the bkgd/ms pin. 2.2.5 adc reference pins (v refh , v refl ) the v refh and v refl pins are the voltage reference high and voltage reference low inputs, respectively, for the adc module. 2.2.6 general-purpose i/o and peripheral ports the mc9s08de60 series series of mcus support up to 53 general-purpose i/o pins and 1 input-only pin, which are shared with on-chip peripheral functions (timers, serial i/o, adc, mscan, etc.). when a port pin is con?ured as a general-purpose output or a peripheral uses the port pin as an output, software can select one of two drive strengths and enable or disable slew rate control. when a port pin is con?ured as a general-purpose input or a peripheral uses the port pin as an input, software can enable a pull-up device. immediately after reset, all of these pins are con?ured as high-impedance general-purpose inputs with internal pull-up devices disabled. when an on-chip peripheral system is controlling a pin, data direction control bits still determine what is read from port data registers even though the peripheral module controls the pin direction by controlling the enable for the pins output buffer. for information about controlling these pins as general-purpose i/o pins, see chapter 6, ?arallel input/output control .
chapter 2 pins and connections mc9s08de60 series data sheet, rev. 3 freescale semiconductor 31 note to avoid extra current drain from ?ating input pins, the reset initialization routine in the application program should either enable on-chip pull-up devices or change the direction of unused or non-bonded pins to outputs so they do not ?at.
chapter 2 pins and connections mc9s08de60 series data sheet, rev. 3 32 freescale semiconductor pin number <-- lowest priority --> highest port pin/interrupt alt 1 alt 2 1 ptb6 pib6 adp14 2 ptc5 adp21 3 pta7 pia7 adp7 irq 4 ptc6 adp22 5 ptb7 pib7 adp15 6 ptc7 adp23 7v dd 8v ss 9 ptg0 extal 10 ptg1 xtal 11 reset 12 ptf4 acmp2+ 13 ptf5 acmp2- 14 ptf6 acmp2o 15 pte0 txd1 16 pte1 2 rxd1 2 17 pte2 ss 18 pte3 spsck 19 pte4 scl 3 mosi 20 pte5 sda 3 miso 21 ptg2 22 ptg3 23 ptf0 txd2 4 24 ptf1 rxd2 4 25 ptf2 tpm1clk scl 3 26 ptf3 tpm2clk sda 3 27 ptg4 28 ptg5 29 pte6 txd2 4 txcan 30 pte7 rxd2 4 rxcan 31 ptd0 pid0 tpm2ch0 32 ptd1 pid1 tpm2ch1 33 ptd2 pid2 tpm1ch0 34 ptd3 pid3 tpm1ch1 35 ptd4 pid4 tpm1ch2 36 ptd5 pid5 tpm1ch3 37 ptf7 38 v ss 39 v dd 40 ptd6 pid6 tpm1ch4 41 ptd7 pid7 tpm1ch5 42 bkgd ms 43 ptc0 adp16 44 ptb0 pib0 adp8 45 ptc1 adp17 46 pta0 pia0 adp0 mclk 47 ptc2 adp18 48 ptb1 pib1 adp9 49 pta1 pia1 adp1 1 acmp1+ 1 50 ptb2 pib2 adp10 51 pta2 pia2 adp2 1 acmp1- 1 52 ptc3 adp19 53 ptb3 pib3 adp11 54 pta3 pia3 adp3 acmp1o 55 v ssa 56 v refl 57 v refh 58 v dda 59 pta4 pia4 adp4 60 ptb4 pib4 adp12 61 ptc4 adp20 62 pta5 pia5 adp5 63 ptb5 pib5 adp13 64 pta6 pia6 adp6 pin number <-- lowest priority --> highest port pin/interrupt alt 1 alt 2 table 2-1. pin availability 1. if both of these analog modules are enabled they both will have access to the pin. 2. pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on this pin when internal pull-up is enabled may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled to v dd . 3. the iic module pins can be repositioned using iicps bit in the sopt1 register. the default reset locations are on ptf2 and ptf3. 4. the sci2 module pins can be repositioned using sci2ps bit in the sopt1 register. the default reset locations are on ptf0 and ptf1.
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 33 chapter 3 modes of operation 3.1 introduction the operating modes of the mc9s08de60 series are described in this chapter. entry into each mode, exit from each mode, and functionality while in each of the modes are described. 3.2 features active background mode for code development wait mode ?cpu shuts down to conserve power; system clocks are running and full regulation is maintained stop modes ?system clocks are stopped and voltage regulator is in standby stop3 ?all internal circuits are powered for fast recovery stop2 ?partial power down of internal circuits; ram content is retained 3.3 run mode this is the normal operating mode for the mc9s08de60 series. this mode is selected when the bkgd/ms pin is high at the rising edge of reset. in this mode, the cpu executes code from internal memory with execution beginning at the address fetched from memory at 0xfffe?xffff after reset. 3.4 active background mode the active background mode functions are managed through the background debug controller (bdc) in the hcs08 core. the bdc, together with the on-chip debug module (dbg), provide the means for analyzing mcu operation during software development. active background mode is entered in any of ve ways: when the bkgd/ms pin is low at the rising edge of reset when a background command is received through the bkgd/ms pin when a bgnd instruction is executed when encountering a bdc breakpoint when encountering a dbg breakpoint after entering active background mode, the cpu is held in a suspended state waiting for serial background commands rather than executing instructions from the user application program.
chapter 3 modes of operation mc9s08de60 series data sheet, rev. 3 34 freescale semiconductor background commands are of two types: non-intrusive commands, de?ed as commands that can be issued while the user program is running. non-intrusive commands can be issued through the bkgd/ms pin while the mcu is in run mode; non-intrusive commands can also be executed when the mcu is in the active background mode. non-intrusive commands include: memory access commands memory-access-with-status commands bdc register access commands the background command active background commands, which can only be executed while the mcu is in active background mode. active background commands include commands to: read or write cpu registers trace one user program instruction at a time leave active background mode to return to the user application program (go) the active background mode is used to program a bootloader or user application program into the flash program memory before the mcu is operated in run mode for the ?st time. when the mc9s08de60 series is shipped from the freescale semiconductor factory, the flash program memory is erased by default unless speci?ally noted so there is no program that could be executed in run mode until the flash memory is initially programmed. the active background mode can also be used to erase and reprogram the flash memory after it has been previously programmed. for additional information about the active background mode, refer to the development support chapter. 3.5 wait mode wait mode is entered by executing a wait instruction. upon execution of the wait instruction, the cpu enters a low-power state in which it is not clocked. the i bit in ccr is cleared when the cpu enters the wait mode, enabling interrupts. when an interrupt request occurs, the cpu exits the wait mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine. while the mcu is in wait mode, there are some restrictions on which background debug commands can be used. only the background command and memory-access-with-status commands are available when the mcu is in wait mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from wait mode and enter active background mode.
chapter 3 modes of operation mc9s08de60 series data sheet, rev. 3 freescale semiconductor 35 3.6 stop modes one of two stop modes is entered upon execution of a stop instruction when the stope bit in sopt1 register is set. in both stop modes, all internal clocks are halted. the mcg module can be con?ured to leave the reference clocks running. see chapter 8, ?ulti-purpose clock generator (s08mcgv1) ,?for more information. table 3-1 shows all of the control bits that affect stop mode selection and the mode selected under various conditions. the selected mode is entered following the execution of a stop instruction. 3.6.1 stop3 mode stop3 mode is entered by executing a stop instruction under the conditions as shown in table 3-1 . the states of all of the internal registers and logic, ram contents, and i/o pin states are maintained. exit from stop3 is done by asserting reset or an asynchronous interrupt pin. the asynchronous interrupt pins are irq, pia0?ia7, pib0?ib7, and pid0?id7. exit from stop3 can also be done by the low-voltage detect (lvd) reset, low-voltage warning (lvw) interrupt, adc conversion complete interrupt, real-time clock (rtc) interrupt, mscan wake-up interrupt, or sci receiver interrupt. if stop3 is exited by means of the reset pin, the mcu will be reset and operation will resume after fetching the reset vector. exit by means of an interrupt will result in the mcu fetching the appropriate interrupt vector. 3.6.1.1 lvd enabled in stop3 mode the lvd system is capable of generating either an interrupt or a reset when the supply voltage drops below the lvd voltage. if the lvd is enabled in stop (lvde and lvdse bits in spmsc1 both set) at the time the cpu executes a stop instruction, then the voltage regulator remains active during stop mode. for the adc to operate the lvd must be left enabled when entering stop3. table 3-1. stop mode selection stope enbdm 1 1 enbdm is located in the bdcscr, which is only accessible through bdc commands, see section 17.4.1.1, ?dc status and control register (bdcscr)? lvde lvdse ppdc stop mode 0 x x x stop modes disabled; illegal opcode reset if stop instruction executed 1 1 x x stop3 with bdm enabled 2 2 when in stop3 mode with bdm enabled, the s idd will be near r idd levels because internal clocks are enabled. 1 0 both bits must be 1 x stop3 with voltage regulator active 1 0 either bit a 0 0 stop3 1 0 either bit a 0 1 stop2
chapter 3 modes of operation mc9s08de60 series data sheet, rev. 3 36 freescale semiconductor 3.6.1.2 active bdm enabled in stop3 mode entry into the active background mode from run mode is enabled if enbdm in bdcscr is set. this register is described in chapter 17, ?evelopment support .?if enbdm is set when the cpu executes a stop instruction, the system clocks to the background debug logic remain active when the mcu enters stop mode. because of this, background debug communication remains possible. in addition, the voltage regulator does not enter its low-power standby state but maintains full internal regulation. most background commands are not available in stop mode. the memory-access-with-status commands do not allow memory access, but they report an error indicating that the mcu is in either stop or wait mode. the background command can be used to wake the mcu from stop and enter active background mode if the enbdm bit is set. after entering background debug mode, all background commands are available. 3.6.2 stop2 mode stop2 mode is entered by executing a stop instruction under the conditions as shown in table 3-1 . most of the internal circuitry of the mcu is powered off in stop2 with the exception of the ram. upon entering stop2, all i/o pin control signals are latched so that the pins retain their states during stop2. exit from stop2 is performed by asserting reset. on 3m05c or older masksets only, exit from stop2 can also be performed by asserting pta7/adp7/irq. note on 3m05c or older masksets only, pta7/adp7/irq is an active low wake-up and must be con?ured as an input prior to executing a stop instruction to avoid an immediate exit from stop2. pta7/adp7/irq can be disabled as a wake-up if it is con?ured as a high driven output. for lowest power consumption in stop2, this pin should not be left open when con?ured as input (enable the internal pullup; or tie an external pullup/down device; or set pin as output). in addition, the real-time counter (rtc) can wake the mcu from stop2, if enabled. upon wake-up from stop2 mode, the mcu starts up as from a power-on reset (por): all module control and status registers are reset the lvd reset function is enabled and the mcu remains in the reset state if v dd is below the lvd trip point (low trip point selected due to por) the cpu takes the reset vector in addition to the above, upon waking up from stop2, the ppdf bit in spmsc2 is set. this ?g is used to direct user code to go to a stop2 recovery routine. ppdf remains set and the i/o pin states remain latched until a 1 is written to ppdack in spmsc2.
chapter 3 modes of operation mc9s08de60 series data sheet, rev. 3 freescale semiconductor 37 to maintain i/o states for pins that were con?ured as general-purpose i/o before entering stop2, the user must restore the contents of the i/o port registers, which have been saved in ram, to the port registers before writing to the ppdack bit. if the port registers are not restored from ram before writing to ppdack, then the pins will switch to their reset states when ppdack is written. for pins that were con?ured as peripheral i/o, the user must recon?ure the peripheral module that interfaces to the pin before writing to the ppdack bit. if the peripheral module is not enabled before writing to ppdack, the pins will be controlled by their associated port control registers when the i/o latches are opened. 3.6.3 on-chip peripheral modules in stop modes when the mcu enters any stop mode, system clocks to the internal peripheral modules are stopped. even in the exception case (enbdm = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. refer to section 3.6.2, ?top2 mode?and section 3.6.1, ?top3 mode ?for speci? information on system behavior in stop modes. table 3-2. stop mode behavior peripheral mode stop2 stop3 cpu off standby ram standby standby flash/eeprom off standby parallel port registers off standby acmp off off adc off optionally on 1 1 requires the asynchronous adc clock and lvd to be enabled, else in standby. iic off standby mcg off optionally on 2 2 irclken and irefsten set in mcgc1, else in standby. mscan off standby rtc optionally on 3 3 requires the rtc to be enabled, else in standby. optionally on 3 sci off standby spi off standby tpm off standby voltage regulator off optionally on 4 4 requires the lvd or bdc to be enabled. xosc off optionally on 5 i/o pins states held states held bdm off 6 optionally on lvd/lvw off 7 optionally on
chapter 3 modes of operation mc9s08de60 series data sheet, rev. 3 38 freescale semiconductor 5 erclken and erefsten set in mcgc2 for, else in standby. for high frequency range (range in mcgc2 set) requires the lvd to also be enabled in stop3. 6 if enbdm is set when entering stop2, the mcu will actually enter stop3. 7 if lvdse is set when entering stop2, the mcu will actually enter stop3.
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 39 chapter 4 memory 4.1 mc9s08de60 series memory map on-chip memory in the mc9s08de60 series consists of ram, eeprom, and flash program memory for nonvolatile data storage, and i/o and control/status registers. the registers are divided into three groups: direct-page registers (0x0000 through 0x007f) high-page registers (0x1800 through 0x18ff) nonvolatile registers (0xffb0 through 0xffbf) figure 4-1. mc9s08de60 memory map direct page registers ram 4096 bytes 0x0000 0x007f 0x0080 0x107f 0x1800 0x17ff 0x18ff 0x1400 0xffff 0x1080 mc9s08de60 128 bytes eeprom 2 x 1024 bytes high page registers 256 bytes flash 59136 bytes direct page registers ram 2048 bytes 0x0000 0x007f 0x0080 0x087f 0x1800 0x17ff 0x18ff 0x1900 0xffff 0x1600 MC9S08DE32 0x7bff 0x7c00 128 bytes high page registers 256 bytes flash 33792 bytes unimplemented 0x0880 0x15ff 3456 bytes unimplemented 25,344 bytes eeprom 2 x 512 bytes 0x1900 flash 896 bytes 0x13ff direct page registers ram 4096 bytes 0x0000 0x007f 0x0080 0x107f 0x1800 0x17ff 0x18ff 0x1400 0xffff 0x1080 mc9s08de60 128 bytes eeprom 2 x 1024 bytes high page registers 256 bytes flash 44,032 bytes 0x1900 unimplemented 896 bytes 0x13ff unimplemented 15,104 bytes 0x5400 0x53ff 0x1900 direct page registers ram 2048 bytes 0x0000 0x007f 0x0080 0x087f 0x1800 0x17ff 0x18ff 0x1900 0xffff 0x1600 MC9S08DE32 0xa7ff 0xa800 128 bytes high page registers 256 bytes flash 22,528 bytes unimplemented 0x0880 0x15ff 3456 bytes unimplemented 38,608 bytes eeprom 2 x 512 bytes ecc disabled ecc disabled ecc enabled ecc enabled 0x1080
chapter 4 memory mc9s08de60 series data sheet, rev. 3 40 freescale semiconductor 4.2 reset and interrupt vector assignments table 4-1 shows address assignments for reset and interrupt vectors. the vector names shown in this table are the labels used in the mc9s08de60 series equate file provided by freescale semiconductor. table 4-1. reset and interrupt vectors address (high/low) vector vector name 0xffc0:0xffc1 acmp2 vacmp2 0xffc2:0xffc3 acmp1 vacmp1 0xffc4:0xffc5 mscan transmit vcantx 0xffc6:0xffc7 mscan receive vcanrx 0xffc8:0xffc9 mscan errors vcanerr 0xffca:0xffcb mscan wake up vcanwu 0xffcc:0xffcd rtc vrtc 0xffce:0xffcf iic viic 0xffd0:0xffd1 adc conversion vadc 0xffd2:0xffd3 port a, port b, port d vport 0xffd4:0xffd5 sci2 transmit vsci2tx 0xffd6:0xffd7 sci2 receive vsci2rx 0xffd8:0xffd9 sci2 error vsci2err 0xffda:0xffdb sci1 transmit vsci1tx 0xffdc:0xffdd sci1 receive vsci1rx 0xffde:0xffdf sci1 error vsci1err 0xffe0:0xffe1 spi vspi 0xffe2:0xffe3 tpm2 over?w vtpm2ovf 0xffe4:0xffe5 tpm2 channel 1 vtpm2ch1 0xffe6:0xffe7 tpm2 channel 0 vtpm2ch0 0xffe8:0xffe9 tpm1 over?w vtpm1ovf 0xffea:0xffeb tpm1 channel 5 vtpm1ch5 0xffec:0xffed tpm1 channel 4 vtpm1ch4 0xffee:0xffef tpm1 channel 3 vtpm1ch3 0xfff0:0xfff1 tpm1 channel 2 vtpm1ch2 0xfff2:0xfff3 tpm1 channel 1 vtpm1ch1 0xfff4:0xfff5 tpm1 channel 0 vtpm1ch0 0xfff6:0xfff7 mcg loss of lock vlol 0xfff8:0xfff9 low-voltage detect vlvd 0xfffa:0xfffb irq virq 0xfffc:0xfffd swi vswi 0xfffe:0xffff reset vreset
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 41 4.3 register addresses and bit assignments the registers in the mc9s08de60 series are divided into these groups: direct-page registers are located in the ?st 128 locations in the memory map; these are accessible with ef?ient direct addressing mode instructions. high-page registers are used much less often, so they are located above 0x1800 in the memory map. this leaves more room in the direct page for more frequently used registers and ram. the nonvolatile register area consists of a block of 16 locations in flash memory at 0xffb0?xffbf. nonvolatile register locations include: nvprot and nvopt are loaded into working registers at reset nvecc determines whether ecc is enabled at reset an 8-byte backdoor comparison key that optionally allows a user to gain controlled access to secure memory because the nonvolatile register locations are flash memory, they must be erased and programmed like other flash memory locations. direct-page registers can be accessed with ef?ient direct addressing mode instructions. bit manipulation instructions can be used to access any bit in any direct-page register. table 4-2 is a summary of all user-accessible direct-page registers and control bits. the direct page registers in table 4-2 can use the more ef?ient direct addressing mode, which requires only the lower byte of the address. because of this, the lower byte of the address in column one is shown in bold text. in table 4-3 and table 4-5 , the whole address in column one is shown in bold. in table 4-2 , table 4-3 , and table 4-5 , the register names in column two are shown in bold to set them apart from the bit names to the right. cells that are not associated with named bits are shaded. a shaded cell with a 0 indicates this unused bit always reads as a 0. shaded cells with dashes indicate unused or reserved bit locations that could read as 1s or 0s.
chapter 4 memory mc9s08de60 series data sheet, rev. 3 42 freescale semiconductor table 4-2. direct-page register summary (sheet 1 of 3) address register name bit 7 654321 bit 0 0x00 00 ptad ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 0x00 01 ptadd ptadd7 ptadd6 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 0x00 02 ptbd ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 0x00 03 ptbdd ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 0x00 04 ptcd ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 0x00 05 ptcdd ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 0x00 06 ptdd ptdd7 ptdd6 ptdd5 ptdd4 ptdd3 ptdd2 ptdd1 ptdd0 0x00 07 ptddd ptddd7 ptddd6 ptddd5 ptddd4 ptddd3 ptddd2 ptddd1 ptddd0 0x00 08 pted pted7 pted6 pted5 pted4 pted3 pted2 pted1 pted0 0x00 09 ptedd ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 ptedd0 0x00 0a ptfd ptfd7 ptfd6 ptfd5 ptfd4 ptfd3 ptfd2 ptfd1 ptfd0 0x00 0b ptfdd ptfdd7 ptfdd6 ptfdd5 ptfdd4 ptfdd3 ptfdd2 ptfdd1 ptfdd0 0x00 0c ptgd 0 0 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 0x00 0d ptgdd 0 0 ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 0x00 0e acmp1sc acme acbgs acf acie aco acope acmod1 acmod0 0x00 0f acmp2sc acme acbgs acf acie aco acope acmod1 acmod0 0x00 10 adcsc1 coco aien adco adch 0x00 11 adcsc2 adact adtrg acfe acfgt 0 0 0x00 12 adcrh 0 0 0 0 adr11 adr10 adr9 adr8 0x00 13 adcrl adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 0x00 14 adccvh 0 0 0 0 adcv11 adcv10 adcv9 adcv8 0x00 15 adccvl adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 0x00 16 adccfg adlpc adiv adlsmp mode adiclk 0x00 17 apctl1 adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 0x00 18 apctl2 adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 0x00 19 apctl3 adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 0x001a 0x001b reserved 0x00 1c irqsc 0 irqpdd irqedg irqpe irqf irqack irqie irqmod 0x001d 0x001f reserved 0x00 20 tpm1sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 21 tpm1cnth bit 15 14 13 12 11 10 9 bit 8 0x00 22 tpm1cntl bit 7 654321 bit 0 0x00 23 tpm1modh bit 15 14 13 12 11 10 9 bit 8 0x00 24 tpm1modl bit 7 654321 bit 0 0x00 25 tpm1c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 26 tpm1c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 27 tpm1c0vl bit 7 654321 bit 0
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 43 0x00 28 tpm1c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 29 tpm1c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 2a tpm1c1vl bit 7 654321 bit 0 0x00 2b tpm1c2sc ch2f ch2ie ms2b ms2a els2b els2a 0 0 0x00 2c tpm1c2vh bit 15 14 13 12 11 10 9 bit 8 0x00 2d tpm1c2vl bit 7 654321 bit 0 0x00 2e tpm1c3sc ch3f ch3ie ms3b ms3a els3b els3a 0 0 0x00 2f tpm1c3vh bit 15 14 13 12 11 10 9 bit 8 0x00 30 tpm1c3vl bit 7 654321 bit 0 0x00 31 tpm1c4sc ch4f ch4ie ms4b ms4a els4b els4a 0 0 0x00 32 tpm1c4vh bit 15 14 13 12 11 10 9 bit 8 0x00 33 tpm1c4vl bit 7 654321 bit 0 0x00 34 tpm1c5sc ch5f ch5ie ms5b ms5a els5b els5a 0 0 0x00 35 tpm1c5vh bit 15 14 13 12 11 10 9 bit 8 0x00 36 tpm1c5vl bit 7 654321 bit 0 0x0037 reserved 0x00 38 sci1bdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 39 sci1bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 3a sci1c1 loops sciswai rsrc m wake ilt pe pt 0x00 3b sci1c2 tie tcie rie ilie te re rwu sbk 0x00 3c sci1s1 tdre tc rdrf idle or nf fe pf 0x00 3d sci1s2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 3e sci1c3 r8 t8 txdir txinv orie neie feie peie 0x00 3f sci1d bit 7 654321 bit 0 0x00 40 sci2bdh lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 0x00 41 sci2bdl sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 0x00 42 sci2c1 loops sciswai rsrc m wake ilt pe pt 0x00 43 sci2c2 tie tcie rie ilie te re rwu sbk 0x00 44 sci2s1 tdre tc rdrf idle or nf fe pf 0x00 45 sci2s2 lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf 0x00 46 sci2c3 r8 t8 txdir txinv orie neie feie peie 0x00 47 sci2d bit 7 654321 bit 0 0x00 48 mcgc1 clks rdiv irefs irclken irefsten 0x00 49 mcgc2 bdiv range hgo lp erefs erclken erefsten 0x00 4a mcgtrm trim 0x00 4b mcgsc lols lock pllst irefst clkst oscinit ftrim 0x00 4c mcgc3 lolie plls cme 0 vdiv 0x004d 0x004f reserved table 4-2. direct-page register summary (sheet 2 of 3) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08de60 series data sheet, rev. 3 44 freescale semiconductor high-page registers, shown in table 4-3 , are accessed much less often than other i/o and control registers so they have been located outside the direct addressable memory space, starting at 0x1800. 0x00 50 spic1 spie spe sptie mstr cpol cpha ssoe lsbfe 0x00 51 spic2 0 0 0 modfen bidiroe 0 spiswai spc0 0x00 52 spibr 0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 0x00 53 spis sprf 0 sptef modf 0 0 0 0 0x0054 reserved 0 0 0 0 0 0 0 0 0x00 55 spid bit 7 654321 bit 0 0x0056 0x0057 reserved 0x00 58 iica ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 0x00 59 iicf mult icr 0x00 5a iicc1 iicen iicie mst tx txak rsta 0 0 0x00 5b iics tcf iaas busy arbl 0 srw iicif rxak 0x00 5c iicd data 0x00 5d iicc2 gcaen adext 0 0 0 ad10 ad9 ad8 0x005e 0x005f reserved 0x00 60 tpm2sc tof toie cpwms clksb clksa ps2 ps1 ps0 0x00 61 tpm2cnth bit 15 14 13 12 11 10 9 bit 8 0x00 62 tpm2cntl bit 7 654321 bit 0 0x00 63 tpm2modh bit 15 14 13 12 11 10 9 bit 8 0x00 64 tpm2modl bit 7 654321 bit 0 0x00 65 tpm2c0sc ch0f ch0ie ms0b ms0a els0b els0a 0 0 0x00 66 tpm2c0vh bit 15 14 13 12 11 10 9 bit 8 0x00 67 tpm2c0vl bit 7 654321 bit 0 0x00 68 tpm2c1sc ch1f ch1ie ms1b ms1a els1b els1a 0 0 0x00 69 tpm2c1vh bit 15 14 13 12 11 10 9 bit 8 0x00 6a tpm2c1vl bit 7 654321 bit 0 0x006b reserved 0x00 6c rtcsc rtif rtclks rtie rtcps 0x00 6d rtccnt rtccnt 0x00 6e rtcmod rtcmod 0x006f reserved 0x0070 0x007f reserved table 4-2. direct-page register summary (sheet 3 of 3) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 45 table 4-3. high-page register summary (sheet 1 of 3) address register name bit 7 654321 bit 0 0x1800 srs por pin cop ilop ilad locs lvd 0 0x1801 sbdfr 0 0 0 0 0 0 0 bdfr 0x1802 sopt1 copt stope sci2ps iicps 0 0 0 0x1803 sopt2 copclks copw 0 adhts 0 mcsel 0x1804 0x1805 reserved 0x1806 sdidh id11 id10 id9 id8 0x1807 sdidl id7 id6 id5 id4 id3 id2 id1 id0 0x1808 reserved 0x1809 spmsc1 lvwf lvwack lvwie lvdre lvdse lvde 0 bgbe 0x180a spmsc2 0 0 lvdv lvwv ppdf ppdack 0 ppdc 0x180b 0x180f reserved 0x1810 dbgcah bit 15 14 13 12 11 10 9 bit 8 0x1811 dbgcal bit 7 654321 bit 0 0x1812 dbgcbh bit 15 14 13 12 11 10 9 bit 8 0x1813 dbgcbl bit 7 654321 bit 0 0x1814 dbgfh bit 15 14 13 12 11 10 9 bit 8 0x1815 dbgfl bit 7 654321 bit 0 0x1816 dbgc dbgen arm tag brken rwa rwaen rwb rwben 0x1817 dbgt trgsel begin 0 0 trg3 trg2 trg1 trg0 0x1818 dbgs af bf armf 0 cnt3 cnt2 cnt1 cnt0 0x1819 0x181f reserved 0x1820 fcdiv divld prdiv8 div 0x1821 fopt keyen fnored epgmod 0 0 0 sec 0x1822 ftstmod 0 mrds 0 0 0 0 0 0x1823 fcnfg 0 epgsel keyacc eccdis 0 0 0 1 0x1824 fprot eps fps 0x1825 fstat fcbef fccf fpviol faccerr 0 fblank 0 0 0x1826 fcmd fcmd 0x1827 0x183f reserved 0x1840 ptape ptape7 ptape6 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 0x1841 ptase ptase7 ptase6 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 0x1842 ptads ptads7 ptads6 ptads5 ptads4 ptads3 ptads2 ptads1 ptads0 0x1843 reserved 0x1844 ptasc 0 0 0 0 ptaif ptaack ptaie ptamod 0x1845 ptaps ptaps7 ptaps6 ptaps5 ptaps4 ptaps3 ptaps2 ptaps1 ptaps0 0x1846 ptaes ptaes7 ptaes6 ptaes5 ptaes4 ptaes3 ptaes2 ptaes1 ptaes0
chapter 4 memory mc9s08de60 series data sheet, rev. 3 46 freescale semiconductor 0x1847 reserved 0x1848 ptbpe ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 0x1849 ptbse ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 0x184a ptbds ptbds7 ptbds6 ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 0x184b reserved 0x184c ptbsc 0 0 0 0 ptbif ptback ptbie ptbmod 0x184d ptbps ptbps7 ptbps6 ptbps5 ptbps4 ptbps3 ptbps2 ptbps1 ptbps0 0x184e ptbes ptbes7 ptbes6 ptbes5 ptbes4 ptbes3 ptbes2 ptbes1 ptbes0 0x184f reserved 0x1850 ptcpe ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 0x1851 ptcse ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 0x1852 ptcds ptcds7 ptcds6 ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 0x1853 0x1857 reserved 0x1858 ptdpe ptdpe7 ptdpe6 ptdpe5 ptdpe4 ptdpe3 ptdpe2 ptdpe1 ptdpe0 0x1859 ptdse ptdse7 ptdse6 ptdse5 ptdse4 ptdse3 ptdse2 ptdse1 ptdse0 0x185a ptdds ptdds7 ptdds6 ptdds5 ptdds4 ptdds3 ptdds2 ptdds1 ptdds0 0x185b reserved 0x185c ptdsc 0 0 0 0 ptdif ptdack ptdie ptdmod 0x185d ptdps ptdps7 ptdps6 ptdps5 ptdps4 ptdps3 ptdps2 ptdps1 ptdps0 0x185e ptdes ptdes7 ptdes6 ptdes5 ptdes4 ptdes3 ptdes2 ptdes1 ptdes0 0x185f reserved 0x1860 ptepe ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 0x1861 ptese ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 ptese0 0x1862 pteds pteds7 pteds6 pteds5 pteds4 pteds3 pteds2 pteds1 pteds0 0x1863 0x1867 reserved 0x1868 ptfpe ptfpe7 ptfpe6 ptfpe5 ptfpe4 ptfpe3 ptfpe2 ptfpe1 ptfpe0 0x1869 ptfse ptfse7 ptfse6 ptfse5 ptfse4 ptfse3 ptfse2 ptfse1 ptfse0 0x186a ptfds ptfds7 ptfds6 ptfds5 ptfds4 ptfds3 ptfds2 ptfds1 ptfds0 0x186b 0x186f reserved 0x1870 ptgpe 0 0 ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 0x1871 ptgse 0 0 ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 0x1872 ptgds 0 0 ptgds5 ptgds4 ptgds3 ptgds2 ptgds1 ptgds0 0x1873 0x187f reserved 0x1880 canctl0 rxfrm rxact cswai synch time wupe slprq initrq 0x1881 canctl1 cane clksrc loopb listen borm wupm slpak initak 0x1882 canbtr0 sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 table 4-3. high-page register summary (sheet 2 of 3) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 47 figure 4-4 shows the structure of receive and transmit buffers for extended identi?r mapping. these registers vary depending on whether standard or extended mapping is selected. see chapter 12, ?reescale controller area network (s08mscanv1) ,?for details on extended and standard identi?r mapping. 0x1883 canbtr1 samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 0x1884 canrflg wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf 0x1885 canrier wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie 0x1886 cantflg 0 0 0 0 0 txe2 txe1 txe0 0x1887 cantier 0 0 0 0 0 txeie2 txeie1 txeie0 0x1888 cantarq 0 0 0 0 0 abtrq2 abtrq1 abtrq0 0x1889 cantaak 0 0 0 0 0 abtak2 abtak1 abtak0 0x188a cantbsel 0 0 0 0 0 tx2 tx1 tx0 0x188b canidac 0 0 idam1 idam0 0 idhit2 idhit1 idhit0 0x188c reserved 0 0 0 0 0 0 0 0 0x188d canmisc 0 0 0 0 0 0 0 bohold 0x188e canrxerr rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 0x188f cantxerr txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 0x1890 0x1893 canidar0 canidar3 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 0x1894 0x1897 canidmr0 canidmr3 am7 am6 am5 am4 am3 am2 am1 am0 0x1898 0x189b canidar4 canidar7 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 0x189c 0x189f canidmr4 canidmr7 am7 am6 am5 am4 am3 am2 am1 am0 0x18be canttsrh tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 0x18bf canttsrl tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 0x18c0 0x18ff reserved table 4-4. mscan foreground receive and transmit buffer layouts ?extended mapping shown 0x18a0 canridr0 id28 id27 id26 id25 id24 id23 id22 id21 0x18a1 canridr1 id20 id19 id18 srr (1) ide (1) id17 id16 id15 0x18a2 canridr2 id14 id13 id12 id11 id10 id9 id8 id7 0x18a3 canridr3 id6 id5 id4 id3 id2 id1 id0 rtr 2 0x18a4 0x18ab canrdsr0 canrdsr7 db7 db6 db5 db4 db3 db2 db1 db0 0x18ac canrdlr dlc3 dlc2 dlc1 dlc0 0x18ad reserved 0x18ae canrtsrh tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 0x18af canrtsrl tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 0x18b0 cantidr0 id10 id9 id8 id7 id6 id5 id4 id3 table 4-3. high-page register summary (sheet 3 of 3) address register name bit 7 654321 bit 0
chapter 4 memory mc9s08de60 series data sheet, rev. 3 48 freescale semiconductor nonvolatile flash registers, shown in table 4-5 , are located in the flash memory. these registers include an 8-byte backdoor key, nvbackkey, which can be used to gain access to secure memory resources. the nvecc register controls whether error correction code is enabled after the next reset. during reset events, the contents of nvprot and nvopt in the nonvolatile register area of the flash memory are transferred into corresponding fprot and fopt working registers in the high-page registers to control security and block protection options. provided the key enable (keyen) bit is 1, the 8-byte comparison key can be used to temporarily disengage memory security. this key mechanism can be accessed only through user code running in secure memory. (a security key cannot be entered directly through background debug commands.) this security key can be disabled completely by programming the keyen bit to 0. if the security key is disabled, the only way to disengage security is by mass erasing the flash if needed (normally through the background debug interface) and verifying that flash is blank. to avoid returning to secure mode after the next reset, program the security bits (sec) to the unsecured state (1:0). 0x18b1 cantidr1 id2 id1 id0 rtr ide 0x18b2 cantidr2 0x18b3 cantidr3 0x18b4 0x18bb cantdsr0 cantdsr7 db7 db6 db5 db4 db3 db2 db1 db0 0x18bc cantdlr dlc3 dlc2 dlc1 dlc0 0x18bd canttbpr prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 1 srr and ide are both 1s. 2 the position of rtr differs between extended and standard identi?r mapping. table 4-5. nonvolatile register summary address register name bit 7 654321 bit 0 0xffae reserved for storage of ftrim 0 0 0 0 0 0 0 ftrim 0xffaf res. for storage of mcgtrm trim 0xffb0 0xffb7 nvbackkey 8-byte comparison key 0xffb8 nvecc ecc7 ecc6 ecc5 ecc4 ecc3 ecc2 ecc1 ecc0 0xffb9 0xffbc reserved 0xffbd nvprot eps fps 0xffbe reserved 0xffbf nvopt keyen fnored epgmod 0 0 0 sec table 4-4. mscan foreground receive and transmit buffer layouts ?extended mapping shown
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 49 4.4 ram the mc9s08de60 series includes static ram. the locations in ram below 0x0100 can be accessed using the more ef?ient direct addressing mode, and any single bit in this area can be accessed with the bit manipulation instructions (bclr, bset, brclr, and brset). locating the most frequently accessed program variables in this area of ram is preferred. the ram retains data while the mcu is in low-power wait, stop2, or stop3 mode. at power-on the contents of ram are uninitialized. ram data is unaffected by any reset if the supply voltage does not drop below the minimum value for ram retention (v ram ). for compatibility with m68hc05 mcus, the hcs08 resets the stack pointer to 0x00ff. in the mc9s08de60 series, it is usually best to reinitialize the stack pointer to the top of the ram so the direct page ram can be used for frequently accessed ram variables and bit-addressable program variables. include the following 2-instruction sequence in your reset initialization routine (where ramlast is equated to the highest address of the ram in the freescale semiconductor equate ?e). ldhx #ramlast+1 ;point one past ram txs ;sp<-(h:x-1) when security is enabled, the ram is considered a secure memory resource and is not accessible through bdm or code executing from non-secure memory. see section 4.5.9, ?ecurity ? for a detailed description of the security feature. 4.5 flash and eeprom mc9s08de60 series devices include flash and eeprom memory intended primarily for program and data storage. in-circuit programming allows the operating program and data to be loaded into flash and eeprom, respectively, after ?al assembly of the application product. it is possible to program the arrays through the single-wire background debug interface. because no special voltages are needed for erase and programming operations, in-application programming is also possible through other software-controlled communication paths. for a more detailed discussion of in-circuit and in-application programming, refer to the hcs08 family reference manual, volume i, freescale semiconductor document order number hcs08rmv1. 4.5.1 features features of the flash and eeprom memory include: array size (see table 1-1 for exact array sizes) optional error correction code (ecc) on flash flash sector size: 768 bytes with ecc off, 512 bytes with ecc on eeprom sector size: selectable 4-byte or 8-byte sector mapping operation single power supply program and erase command interface for fast program and erase operation up to 100,000 program/erase cycles at typical voltage and temperature flexible block protection and vector redirection
chapter 4 memory mc9s08de60 series data sheet, rev. 3 50 freescale semiconductor security feature for flash, eeprom, and ram burst programming capability sector erase abort 4.5.2 program and erase times before any program or erase command can be accepted, the flash and eeprom clock divider register (fcdiv) must be written to set the internal clock for the flash and eeprom module to a frequency (f fclk ) between 150 khz and 200 khz (see section 4.5.12.1, ?lash and eeprom clock divider register (fcdiv) ?. this register can be written only once, so normally this write is performed during reset initialization. the user must ensure that faccerr is not set before writing to the fcdiv register. one period of the resulting clock (1/f fclk ) is used by the command processor to time program and erase pulses. an integer number of these timing pulses is used by the command processor to complete a program or erase command. table 4-6 shows program and erase times. the bus clock frequency and fcdiv determine the frequency of fclk (f fclk ). the time for one cycle of fclk is t fclk = 1/f fclk . the times are shown as a number of cycles of fclk and as an absolute time for the case where t fclk =5s. program and erase times shown include overhead for the command state machine and enabling and disabling of program and erase voltages. 4.5.3 program and erase command execution the fcdiv register must be initialized after any reset and any error ?g is cleared before beginning command execution. the command execution steps are: 1. write a data value to an address in the flash or eeprom array. the address and data information from this write is latched into the flash and eeprom interface. this write is a required ?st step in any command sequence. for erase and blank check commands, the value of the data is not important. for sector erase commands, the address can be any address in the sector of flash or eeprom to be erased. for mass erase and blank check commands, the address can be any address in the flash or eeprom memory. flash and eeprom erase independently of each other. table 4-6. program and erase times parameter cycles of fclk time if fclk = 200 khz byte program 9 45 s burst program 4 20 s 1 1 excluding start/end overhead sector erase 4000 20 ms mass erase 20,000 100 ms sector erase abort 4 20 s 1
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 51 note before programming a particular byte in the flash or eeprom, the sector in which that particular byte resides must be erased by a mass or sector erase operation. reprogramming bits in an already programmed byte without ?st performing an erase operation may disturb data stored in the flash or eeprom memory. 2. write the command code for the desired command to fcmd. the six valid commands are blank check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase 1 (0x41), and sector erase abort (0x47). the command code is latched into the command buffer. 3. write a 1 to the fcbef bit in fstat to clear fcbef and launch the command (including its address and data information). a partial command sequence can be aborted manually by writing a 0 to fcbef any time after the write to the memory array and before writing the 1 that clears fcbef and launches the complete command. aborting a command in this way sets the faccerr access error ?g which must be cleared before starting a new command. a strictly monitored procedure must be obeyed or the command will not be accepted. this minimizes the possibility of any unintended changes to the memory contents. the command complete ?g (fccf) indicates when a command is complete. the command sequence must be completed by clearing fcbef to launch the command. figure 4-2 is a ?wchart for executing all of the commands except for burst programming and sector erase abort. 4. wait until the fccf bit in fstat is set. as soon as fccf= 1, the operation has completed successfully. 1. a mass erase is possible only when the flash block is fully unprotected.
chapter 4 memory mc9s08de60 series data sheet, rev. 3 52 freescale semiconductor figure 4-2. program and erase flowchart 4.5.4 burst program execution the burst program command is used to program sequential bytes of data in less time than would be required using the standard program command. this is possible because the high voltage to the flash array does not need to be disabled between program operations. ordinarily, when a program or erase command is issued, an internal charge pump associated with the flash memory must be enabled to supply high voltage to the array. upon completion of the command, the charge pump is turned off. when a burst program command is issued, the charge pump is enabled and remains enabled after completion of the burst program operation if these two conditions are met: the next burst program command sequence has begun before the fccf bit is set. the next sequential address selects a byte on the same burst block as the current byte being programmed. a burst block in this flash memory consists of 32 bytes. a new burst block begins at each 32-byte address boundary. the ?st byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. subsequent bytes will program in the burst start write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 0 faccerr? clear error faccerr? write to fcdiv (1) (1) required only once after reset. program and erase flow write to flash or eeprom to buffer address and data
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 53 program time provided that the conditions above are met. if the next sequential address is the beginning of a new row, the program time for that byte will be the standard time instead of the burst time. this is because the high voltage to the array must be disabled and then enabled again. if a new burst command has not been queued before the current command completes, then the charge pump will be disabled and high voltage removed from the array. a flowchart to execute the burst program operation is shown in figure 4-3 . figure 4-3. burst program flowchart 1 0 fcbef? start write to flash to buffer address and data write command to fcmd no yes fpviol or write 1 to fcbef to launch command and clear fcbef (2) no yes new burst command? 1 0 fccf? error exit done (2) wait at least four bus cycles before checking fcbef or fccf. 1 0 faccerr? clear error faccerr? write to fcdiv (1) (1) required only once after reset. burst program flow
chapter 4 memory mc9s08de60 series data sheet, rev. 3 54 freescale semiconductor 4.5.5 sector erase abort the sector erase abort operation will terminate the active sector erase operation so that other sectors are available for read and program operations without waiting for the sector erase operation to complete. the sector erase abort command write sequence is as follows: 1. write to any flash or eeprom address to start the command write sequence for the sector erase abort command. the address and data written are ignored. 2. write the sector erase abort command, 0x47, to the fcmd register. 3. clear the fcbef ?g in the fstat register by writing a 1 to fcbef to launch the sector erase abort command. if the sector erase abort command is launched resulting in the early termination of an active sector erase operation, the faccerr flag will set once the operation completes as indicated by the fccf flag being set. the faccerr flag sets to inform the user that the flash sector may not be fully erased and a new sector erase command must be launched before programming any location in that specific sector. if the sector erase abort command is launched but the active sector erase operation completes normally, the faccerr flag will not set upon completion of the operation as indicated by the fccf flag being set. therefore, if the faccerr flag is not set after the sector erase abort command has completed, a sector being erased when the abort command was launched will be fully erased. a flowchart to execute the sector erase abort operation is shown in figure 4-4 . figure 4-4. sector erase abort flowchart start write 0x47 to fcmd write 1 to fcbef to launch command and clear fcbef (2) 1 0 fccf? sector erase aborted (2) wait at least four bus cycles 0 1 fccf? write to flash to buffer address and data faccerr? 0 1 sector erase completed before checking fcbef or fccf. sector erase abort flow
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 55 note the fcbef ?g will not set after launching the sector erase abort command. if an attempt is made to start a new command write sequence with a sector erase abort operation active, the faccerr ?g in the fstat register will be set. a new command write sequence may be started after clearing the accerr ?g, if set. note the sector erase abort command should be used sparingly since a sector erase operation that is aborted counts as a complete program/erase cycle. 4.5.6 access errors an access error occurs whenever the command execution protocol is violated. any of the following speci? actions will cause the access error ?g (faccerr) in fstat to be set. faccerr must be cleared by writing a 1 to faccerr in fstat before any command can be processed. writing to a flash address before the internal flash and eeprom clock frequency has been set by writing to the fcdiv register. writing to a flash address while fcbef is not set. (a new command cannot be started until the command buffer is empty.) writing a second time to a flash address before launching the previous command. (there is only one write to flash for every command.) writing a second time to fcmd before launching the previous command. (there is only one write to fcmd for every command.) writing to any flash control register other than fcmd after writing to a flash address. writing any command code other than the six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or 0x47) to fcmd. writing any flash control register other than to write to fstat (to clear fcbef and launch the command) after writing the command to fcmd. the mcu enters stop mode while a program or erase command is in progress. (the command is aborted.) writing the byte program, burst program, sector erase or sector erase abort command code (0x20, 0x25, 0x40, or 0x47) with a background debug command while the mcu is secured. (the background debug controller can do blank check and mass erase commands only when the mcu is secure.) writing 0 to fcbef to cancel a partial command.
chapter 4 memory mc9s08de60 series data sheet, rev. 3 56 freescale semiconductor 4.5.7 block protection the block protection feature prevents the protected region of flash or eeprom from program or erase changes. block protection is controlled through the flash and eeprom protection register (fprot). the eps bits determine the protected region of eeprom and the fps bits determine the protected region of flash. see section 4.5.12.5, ?lash and eeprom protection register (fprot and nvprot) . after exit from reset, fprot is loaded with the contents of the nvprot location, which is in the nonvolatile register block of the flash memory. any fprot write that attempts to decrease the size of the protected region will be ignored. because nvprot is within the last sector of flash, if any amount of memory is protected, nvprot is itself protected and cannot be unprotected (intentionally or unintentionally) by the application software. fprot can be written through background debug commands, which provides a way to erase and reprogram protected flash memory. one use for block protection is to block protect an area of flash memory for a bootloader program. this bootloader program can call a routine outside of flash that can be used to sector erase the rest of the flash memory and reprogram it. the bootloader is protected even if mcu power is lost during an erase and reprogram operation. 4.5.8 vector redirection while any flash is block protected, the reset and interrupt vectors will be protected. vector redirection allows users to modify interrupt vector information without unprotecting bootloader and reset vector space. vector redirection is enabled by programming the fnored bit in the nvopt register located at address 0xffbf to 0. for redirection to occur, at least some portion of the flash memory must be block protected by programming the nvprot register located at address 0xffbd. all interrupt vectors (memory locations 0xffc0?xfffd) are redirected, though the reset vector (0xfffe:0xffff) is not. for example, if 1536 bytes of flash are protected, the protected address region is from 0xfa00 through 0xffff. the interrupt vectors (0xffc0?xfffd) are redirected to the locations 0xf9c0?xf9fd. if vector redirection is enabled and an interrupt occurs, the values in the locations 0xf9e0:0xf9e1 are used for the vector instead of the values in the locations 0xffe0:0xffe1. this allows the user to reprogram the unprotected portion of the flash with new program code including new interrupt vector values while leaving the protected area, which includes the default vector locations, unchanged. 4.5.9 security the mc9s08de60 series includes circuitry to prevent unauthorized access to the contents of flash, eeprom, and ram memory. when security is engaged, flash, eeprom, and ram are considered secure resources. direct-page registers, high-page registers, and the background debug controller are considered unsecured resources. programs executing within secure memory have normal access to any mcu memory locations and resources. attempts to access a secure memory location with a program executing from an unsecured memory space or through the background debug interface are blocked (writes are ignored and reads return all 0s). security is engaged or disengaged based on the state of two register bits (sec[1:0]) in the fopt register. during reset, the contents of the nonvolatile location nvopt are copied from flash into the working fopt register in high-page register space. a user engages security by programming the nvopt location,
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 57 which can be performed at the same time the flash memory is programmed. the 1:0 state disengages security; the other three combinations engage security. notice the erased state (1:1) makes the mcu secure. during development, whenever the flash is erased, it is good practice to immediately program the sec0 bit to 0 in nvopt so sec = 1:0. this would allow the mcu to remain unsecured after a subsequent reset. the on-chip debug module cannot be enabled while the mcu is secure. the separate background debug controller can be used for background memory access commands, but the mcu cannot enter active background mode except by holding bkgd low at the rising edge of reset. a user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. if the nonvolatile keyen bit in nvopt/fopt is 0, the backdoor key is disabled and there is no way to disengage security without completely erasing all flash locations. if keyen is 1, a secure user program can temporarily disengage security by: 1. writing 1 to keyacc in the fcnfg register. this makes the flash module interpret writes to the backdoor comparison key locations (nvbackkey through nvbackkey+7) as values to be compared against the key rather than as the ?st step in a flash program or erase command. 2. writing the user-entered key values to the nvbackkey through nvbackkey+7 locations. these writes must be performed in order starting with the value for nvbackkey and ending with nvbackkey+7. sthx must not be used for these writes because these writes cannot be performed on adjacent bus cycles. user software normally would get the key codes from outside the mcu system through a communication interface such as a serial i/o. 3. writing 0 to keyacc in the fcnfg register. if the 8-byte key that was written matches the key stored in the flash locations, sec bits are automatically changed to 1:0 and security will be disengaged until the next reset. the security key can be written only from secure memory (either ram, eeprom, or flash), so it cannot be entered through background commands without the cooperation of a secure user program. the backdoor comparison key (nvbackkey through nvbackkey+7) is located in flash memory locations in the nonvolatile register space so users can program these locations exactly as they would program any other flash memory location. the nonvolatile registers are in the same 768-byte block of flash as the reset and interrupt vectors, so block protecting that space also block protects the backdoor comparison key. block protects cannot be changed from user application programs, so if the vector space is block protected, the backdoor security key mechanism cannot permanently change the block protect, security settings, or the backdoor key. security can always be disengaged through the background debug interface by taking these steps: 1. disable any block protections by writing fprot. fprot can be written only with background debug commands, not from application software. 2. mass erase flash if necessary. 3. blank check flash. provided flash is completely erased, security is disengaged until the next reset. to avoid returning to secure mode after the next reset, program nvopt so sec = 1:0.
chapter 4 memory mc9s08de60 series data sheet, rev. 3 58 freescale semiconductor 4.5.10 error correction code the flash memory includes error correction code (ecc) logic that implements hamming code to correct single bit faults during all flash array read operations. ecc is an optional feature that can be enabled by programming the nvecc con?uration byte, such that upon the next reset, the eccdis con?uration bit will read zero and thus enabling ecc. 4.5.10.1 enable ecc fully erased parts default to ecc disabled for main reads and programs (nvecc = 0xff). to enable ecc in user mode, users need to program nvecc to 0x66, then pull a reset to execute the reset sequence that would clear eccdis. the ecc parity code for 0x66 is 0xf so if users ever read the nvecc location after ecc is turned on, they will get a valid ecc result even though the original byte was programmed with ecc off. when nvecc is read during the reset sequence with ecc off, if either nibble of nvecc is 0x6, then ecc is enabled. even though the parity bits are ignored, a single bit fault will not prevent a programmed nvecc from enabling ecc and a single bit fault will not prevent an erased nvecc from disabling ecc. the eccdis bit will be based on the contents of nvecc read during the reset sequence. when a part is first programmed through the background debug controller, the programmer is able to write to the eccdis bit to enable ecc if desired and then program the entire s-record file including nvecc. 4.5.10.2 ecc remapping the ecc logic implements a single-bit correction method which stores four parity bits per eight data bit. the array architecture of the flash allows for one third of the code storage bits to be used as ecc parity bits when ecc is turned on. the flash sector size becomes 512 bytes when ecc is enabled and the entire array is remapped yielding a continuous address range across sectors. 4.5.11 eeprom mapping only half of the eeprom is in the memory map. the epgsel bit in fcnfg register selects which half of the array can be accessed in foreground while the other half can not be accessed in background. there are two mapping mode options that can be selected to con?ure the 8-byte eeprom sectors: 4-byte mode and 8-byte mode. each mode is selected by the epgmod bit in the fopt register. in 4-byte sector mode (epgmod = 0), each 8-byte sector splits four bytes on foreground and four bytes on background but on the same addresses. the epgsel bit selects which four bytes can be accessed. during a sector erase, the entire 8-byte sector (four bytes in foreground and four bytes in background) is erased. in 8-byte sector mode (epgmod = 1), each entire 8-byte sector is in a single page. the epgsel bit selects which sectors are on background. during a sector erase, the entire 8-byte sector in foreground is erased. 4.5.12 flash and eeprom registers and control bits the flash and eeprom modules have seven 8-bit registers in the high-page register space and three locations in the nonvolatile register space in flash memory. two of those locations are copied into two
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 59 corresponding high-page control registers at reset. there is also an 8-byte comparison key in flash memory. refer to table 4-3 and table 4-5 for the absolute address assignments for all flash and eeprom registers. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or header ?e normally is used to translate these names into the appropriate absolute addresses. 4.5.12.1 flash and eeprom clock divider register (fcdiv) bit 7 of this register is a read-only ?g. bits 6:0 may be read at any time but can be written only one time. before any erase or programming operations are possible, write to this register to set the frequency of the clock for the nonvolatile memory system within acceptable limits. if prdiv8 = 0 ?f fclk = f bus (div + 1) eqn. 4-1 if prdiv8 = 1 ?f fclk = f bus (8 (div + 1)) eqn. 4-2 table 4-8 shows the appropriate values for prdiv8 and div for selected bus frequencies. 76543210 r divld prdiv8 div w reset 00000000 = unimplemented or reserved figure 4-5. flash and eeprom clock divider register (fcdiv) table 4-7. fcdiv register field descriptions field description 7 divld divisor loaded status flag when set, this read-only status ?g indicates that the fcdiv register has been written since reset. reset clears this bit and the ?st write to this register causes this bit to become set regardless of the data written. 0 fcdiv has not been written since reset; erase and program operations disabled for flash and eeprom. 1 fcdiv has been written since reset; erase and program operations enabled for flash and eeprom. 6 prdiv8 prescale (divide) flash and eeprom clock by 8 (this bit is write once.) 0 clock input to the flash and eeprom clock divider is the bus rate clock. 1 clock input to the flash and eeprom clock divider is the bus rate clock divided by 8. 5:0 div divisor for flash and eeprom clock divider these bits are write once. the flash and eeprom clock divider divides the bus rate clock (or the bus rate clock divided by 8 if prdiv8 = 1) by the value in the 6-bit div ?ld plus one. the resulting frequency of the internal flash and eeprom clock must fall within the range of 200 khz to 150 khz for proper flash and eeprom operations. program/erase timing pulses are one cycle of this internal flash and eeprom clock which corresponds to a range of 5 s to 6.7 s. the automated programming logic uses an integer number of these pulses to complete an erase or program operation. see equation 4-1 and equation 4-2 .
chapter 4 memory mc9s08de60 series data sheet, rev. 3 60 freescale semiconductor 4.5.12.2 flash and eeprom options register (fopt and nvopt) during reset, the contents of the nonvolatile location nvopt are copied from flash into fopt. to change the value in this register, erase and reprogram the nvopt location in flash memory as usual and then issue a new mcu reset. table 4-8. flash and eeprom clock divider settings f bus prdiv8 (binary) div (decimal) f fclk program/erase timing pulse (5 s min, 6.7 s max) 20 mhz 1 12 192.3 khz 5.2 s 10 mhz 0 49 200 khz 5 s 8 mhz 0 39 200 khz 5 s 4 mhz 0 19 200 khz 5 s 2 mhz 0 9 200 khz 5 s 1 mhz 0 4 200 khz 5 s 200 khz 0 0 200 khz 5 s 150 khz 0 0 150 khz 6.7 s 76543210 r keyen fnored epgmod 0 0 0 sec w reset f f f 0 0 0 f f = unimplemented or reserved f = loaded from nonvolatile location nvopt during reset figure 4-6. flash and eeprom options register (fopt) table 4-9. fopt register field descriptions field description 7 keyen backdoor key mechanism enable ?when this bit is 0, the backdoor key mechanism cannot be used to disengage security. the backdoor key mechanism is accessible only from user (secured) ?mware. bdm commands cannot be used to write key comparison values that would unlock the backdoor key. for more detailed information about the backdoor key mechanism, refer to section 4.5.9, ?ecurity . 0 no backdoor key access allowed. 1 if user ?mware writes an 8-byte value that matches the nonvolatile backdoor key (nvbackkey through nvbackkey+7 in that order), security is temporarily disengaged until the next mcu reset. 6 fnored vector redirection disable ?when this bit is 1, then vector redirection is disabled. 0 vector redirection enabled. 1 vector redirection disabled.
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 61 4.5.12.3 flash and eeprom test mode register (ftstmod) 5 epgmod eeprom sector mode when this bit is 0, each sector is split into two pages (4-byte mode). when this bit is 1, each sector is in a single page (8-byte mode). 0 half of each eeprom sector is in page 0 and the other half is in page 1. 1 each sector is in a single page. 1:0 sec security state code this 2-bit ?ld determines the security state of the mcu as shown in table 4-10 . when the mcu is secure, the contents of ram, eeprom and flash memory cannot be accessed by instructions from any unsecured source including the background debug interface. sec changes to 1:0 after successful backdoor key entry or a successful blank check of flash. for more detailed information about security, refer to section 4.5.9, ?ecurity . table 4-10. security states 1 1 sec changes to 1:0 after successful backdoor key entry or a successful blank check of flash. sec[1:0] description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure 76543210 r0 mrds 00000 w reset 00000000 = unimplemented or reserved figure 4-7. flash and eeprom test mode register (ftstmod) table 4-11. ftstmod register field descriptions field description 6:5 mrds margin read setting ?these bits are used to set the margin level of the sense ampli?rs for flash and eeprom read operations. 00 normal 01 program margin 1 10 erase margin 2 11 normal 1 flash and eeprom array reads will be sensitive to program margin. 2 flash and eeprom array reads will be sensitive to erase margin. table 4-9. fopt register field descriptions field description
chapter 4 memory mc9s08de60 series data sheet, rev. 3 62 freescale semiconductor 4.5.12.4 flash and eeprom con?uration register (fcnfg) 4.5.12.5 flash and eeprom protection register (fprot and nvprot) the fprot register de?es which flash and eeprom sectors are protected against program and erase operations. during the reset sequence, the fprot register is loaded from the nonvolatile location nvprot. to change the protection that will be loaded during the reset sequence, the sector containing nvprot must be unprotected and erased, then nvprot can be reprogrammed. fprot bits are readable at any time and writable as long as the size of the protected region is being increased. any write to fprot that attempts to decrease the size of the protected memory will be ignored. trying to alter data in any protected area will result in a protection violation error and the fpviol ?g will be set in the fstat register. mass erase is not possible if any one of the sectors is protected. 76543210 r0 epgsel keyacc eccdis 0000 w reset 0 0 0 f 1 1 during reset this bit is decoded from the non-volatile nvecc register. 0000 = unimplemented or reserved figure 4-8. flash and eeprom con?uration register (fcnfg) table 4-12. fcnfg register field descriptions field description 6 epgsel eeprom page select ?this bit selects which eeprom page is accessed in the memory map. 0 page 0 is in foreground of memory map. page 1 is in background and can not be accessed. 1 page 1 is in foreground of memory map. page 0 is in background and can not be accessed. 5 keyacc enable writing of access key ?this bit enables writing of the backdoor comparison key. for more detailed information about the backdoor key mechanism, refer to section 4.5.9, ?ecurity . 0 writes to 0xffb0?xffb7 are interpreted as the start of a flash programming or erase command. 1 writes to nvbackkey (0xffb0?xffb7) are interpreted as comparison key writes. 4 eccdis error correction code disable ?this bit indicates if ecc is enabled or disabled for flash. this bit can only be written in active background mode. see section 4.5.10.1, ?nable ecc ? 0 ecc is enabled. 1 ecc is disabled.
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 63 figure 4-9. flash and eeprom protection register (fprot) 76543210 r eps 1 1 background commands can be used to change the contents of these bits in fprot. fps 1 w reset this register is loaded from nonvolatile location nvprot during reset. table 4-13. fprot register field descriptions field description 7:6 eps eeprom protect select bits ?this 2-bit ?ld determines the protected eeprom locations that cannot be erased or programmed. see table 4-14 . 5:0 fps flash protect select bits this 6-bit ?ld determines the protected flash locations that cannot be erased or programmed. see table 4-15table 4-16 . table 4-14. eeprom block protection eps address area protected memory size protected (bytes) number of sectors protected 0x3 n/a 0 0 0x2 0x17f0 - 0x17ff 32 4 0x1 0x17e0 - 0x17ff 64 8 0x0 0x17c0?x17ff 128 16 table 4-15. mc9s08de60 flash block protection fps address area protected memory size protected (bytes) number of sectors protected ecc off ecc on ecc off ecc on ecc off ecc on 0x3f n/a 0 0 0 0x3e 0xfa00?xffff 1.5k 2 3 0x3d 0xf400?xffff 3k 4 6 0x3c 0xee00?xffff 4.5k 6 9 0x3b 0xe800?xffff 6k 8 12 0x3a 0xe200?xffff 7.5k 10 15 ... ... ... ... 0x2d 0x9400?xffff 27k 36 54 0x2c 0x8e00?xffff 28.5k 38 57 0x2b 0x8800?xffff 30k 40 60 0x2a 0x8200?xffff 31.5k 42 63 0x29 0x7c00?xffff 33k 44 66
chapter 4 memory mc9s08de60 series data sheet, rev. 3 64 freescale semiconductor ... ... ... ... 0x25 0x6400?xffff 39k 52 78 0x24 0x5e00?xffff 40.5k 54 81 0x23 0x5800?xffff 42k 56 84 0x22 0x5200?xffff 0x5400?xffff 43.5k 43k 58 86 0x21 0x4c00?xffff 45k 60 0x20 0x4600?xffff 46.5k 62 0x1f 0x4000?xffff 46.5k 62 ... ... ... ... 0x1b 0x2800?xffff 0x5400?xffff 54k 43k 72 86 0x1a 0x2200?xffff 55.5k 74 0x19 0x1c00?xffff 57k 76 0x18?x00 0x0000?xffff 64k 86 table 4-15. mc9s08de60 flash block protection fps address area protected memory size protected (bytes) number of sectors protected ecc off ecc on ecc off ecc on ecc off ecc on
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 65 table 4-16. MC9S08DE32 flash block protection fps address area protected memory size protected (bytes) number of sectors protected ecc off ecc on ecc off ecc on ecc off ecc on 0x3f n/a 0 0 0 0x3e 0xfa00?xffff 1.5k 2 3 0x3d 0xf400?xffff 3k 4 6 0x3c 0xee00?xffff 4.5k 6 9 0x3b 0xe800?xffff 6k 8 12 0x3a 0xe200?xffff 7.5k 10 15 0x39 0xdc00?xffff 9k 12 18 0x38 0xd600?xffff 10.5k 14 21 0x37 0xd000?xffff 12k 16 24 0x36 0xca00?xffff 13.5k 18 27 0x35 0xc400?xffff 15k 20 30 0x34 0xbe00?xffff 16.5k 22 33 0x33 0xb800?xffff 18k 24 36 0x32 0xb200?xffff 19.5k 26 39 0x31 0xac00?xffff 21k 28 42 0x30 0xa600?xffff 0xa800?xffff 22.5k 22k 30 44 0x2f 0xa000?xffff 24k 32 0x2e 0x9a00?xffff 25.5k 34 0x2d 0x9400?xffff 27k 36 0x2c 0x8e00?xffff 28.5k 38 0x2b 0x8800?xffff 30k 40 0x2a 0x8200?xffff 31.5k 42 0x29?x00 0x7c00?xffff 33k 44
chapter 4 memory mc9s08de60 series data sheet, rev. 3 66 freescale semiconductor 4.5.12.6 flash and eeprom status register (fstat) 4.5.12.7 flash and eeprom command register (fcmd) only six command codes are recognized in normal user modes, as shown in table 4-18 . all other command codes are illegal and generate an access error. refer to section 4.5.3, ?rogram and erase 76543210 r fcbef fccf fpviol faccerr 0 fblank 0 0 w reset 11000000 = unimplemented or reserved figure 4-10. flash and eeprom status register (fstat) table 4-17. fstat register field descriptions field description 7 fcbef command buffer empty flag ?the fcbef bit is used to launch commands. it also indicates that the command buffer is empty so that a new command sequence can be executed when performing burst programming. the fcbef bit is cleared by writing a 1 to it or when a burst program command is transferred to the array for programming. only burst program commands can be buffered. 0 command buffer is full (not ready for additional commands). 1 a new burst program command can be written to the command buffer. 6 fccf command complete flag fccf is set automatically when the command buffer is empty and no command is being processed. fccf is cleared automatically when a new command is started (by writing 1 to fcbef to register a command). writing to fccf has no meaning or effect. 0 command in progress 1 all commands complete 5 fpviol protection violation flag fpviol is set automatically when a command that attempts to erase or program a location in a protected block is launched (the erroneous command is ignored). fpviol is cleared by writing a 1 to fpviol. 0 no protection violation. 1 an attempt was made to erase or program a protected location. 4 faccerr access error flag faccerr is set automatically when the proper command sequence is not obeyed exactly (the erroneous command is ignored), if a program or erase operation is attempted before the fcdiv register has been initialized, or if the mcu enters stop while a command was in progress. for a more detailed discussion of the exact actions that are considered access errors, see section 4.5.6, ?ccess errors . faccerr is cleared by writing a 1 to faccerr. writing a 0 to faccerr has no meaning or effect. 0 no access error. 1 an access error has occurred. 2 fblank veri?d as all blank (erased) flag fblank is set automatically at the conclusion of a blank check command if the entire flash or eeprom array was veri?d to be erased. fblank is cleared by clearing fcbef to write a new valid command. writing to fblank has no meaning or effect. 0 after a blank check command is completed and fccf = 1, fblank = 0 indicates the flash or eeprom array is not completely erased. 1 after a blank check command is completed and fccf = 1, fblank = 1 indicates the flash or eeprom array is completely erased (all 0xffff).
chapter 4 memory mc9s08de60 series data sheet, rev. 3 freescale semiconductor 67 command execution ,?for a detailed discussion of flash and eeprom programming and erase operations. it is not necessary to perform a blank check command after a mass erase operation. only blank check is required as part of the security unlocking mechanism. 76543210 r00000000 w fcmd reset 00000000 figure 4-11. flash and eeprom command register (fcmd) table 4-18. flash and eeprom commands command fcmd equate file label blank check 0x05 mblank byte program 0x20 mbyteprog burst program 0x25 mburstprog sector erase 0x40 msectorerase mass erase 0x41 mmasserase sector erase abort 0x47 meraseabort
chapter 4 memory mc9s08de60 series data sheet, rev. 3 68 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 69 chapter 5 resets, interrupts, and general system control 5.1 introduction this section discusses basic reset and interrupt mechanisms and their various sources in the mc9s08de60 series. some interrupt sources from peripheral modules are discussed in greater detail within other sections of this data sheet. this section gathers basic information about all reset and interrupt sources in one place for easy reference. a few reset and interrupt sources, including the computer operating properly (cop) watchdog, are not part of on-chip peripheral systems with their own chapters. 5.2 features reset and interrupt features include: multiple sources of reset for ?xible system con?uration and reliable operation reset status register (srs) to indicate source of most recent reset separate interrupt vector for each module (reduces polling overhead); see table 5-1 5.3 mcu reset resetting the mcu provides a way to start processing from a known set of initial conditions. during reset, most control and status registers are forced to initial values and the program counter is loaded from the reset vector (0xfffe:0xffff). on-chip peripheral modules are disabled and i/o pins are initially con?ured as general-purpose high-impedance inputs with pull-up devices disabled. the i bit in the condition code register (ccr) is set to block maskable interrupts so the user program has a chance to initialize the stack pointer (sp) and system control settings. (see the cpu chapter for information on the interrupt (i) bit.) sp is forced to 0x00ff at reset. the mc9s08de60 series has eight sources for reset: power-on reset (por) external pin reset (pin) computer operating properly (cop) timer illegal opcode detect (ilop) illegal address detect (ilad) low-voltage detect (lvd) loss of clock (loc) background debug forced reset (bdfr) each of these sources, with the exception of the background debug forced reset, has an associated bit in the system reset status register (srs).
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 70 freescale semiconductor 5.4 computer operating properly (cop) watchdog the cop watchdog is intended to force a system reset when the application software fails to execute as expected. to prevent a system reset from the cop timer (when it is enabled), application software must reset the cop counter periodically. if the application program gets lost and fails to reset the cop counter before it times out, a system reset is generated to force the system back to a known starting point. after any reset, the cop watchdog is enabled (see section 5.8.4, ?ystem options register 1 (sopt1) , for additional information). if the cop watchdog is not used in an application, it can be disabled by clearing copt bits in sopt1. the cop counter is reset by writing 0x55 and 0xaa (in this order) to the address of srs during the selected timeout period. writes do not affect the data in the read-only srs. as soon as the write sequence is done, the cop timeout period is restarted. if the program fails to do this during the time-out period, the mcu will reset. also, if any value other than 0x55 or 0xaa is written to srs, the mcu is immediately reset. the copclks bit in sopt2 (see section 5.8.5, ?ystem options register 2 (sopt2) ,?for additional information) selects the clock source used for the cop timer. the clock source options are either the bus clock or an internal 1-khz clock source. with each clock source, there are three associated time-outs controlled by the copt bits in sopt1. table 5-6 summaries the control functions of the copclks and copt bits. the cop watchdog defaults to operation from the 1-khz clock source and the longest time-out (2 10 cycles). when the bus clock source is selected, windowed cop operation is available by setting copw in the sopt2 register. in this mode, writes to the srs register to clear the cop timer must occur in the last 25% of the selected timeout period. a premature write immediately resets the mcu. when the 1-khz clock source is selected, windowed cop operation is not available. the cop counter is initialized by the ?st writes to the sopt1 and sopt2 registers and after any system reset. subsequent writes to sopt1 and sopt2 have no effect on cop operation. even if the application will use the reset default settings of copt, copclks, and copw bits, the user should write to the write-once sopt1 and sopt2 registers during reset initialization to lock in the settings. this will prevent accidental changes if the application program gets lost. the write to srs that services (clears) the cop counter should not be placed in an interrupt service routine (isr) because the isr could continue to be executed periodically even if the main application program fails. if the bus clock source is selected, the cop counter does not increment while the mcu is in background debug mode or while the system is in stop mode. the cop counter resumes when the mcu exits background debug mode or stop mode. if the 1-khz clock source is selected, the cop counter is re-initialized to zero upon entry to either background debug mode or stop mode and begins from zero upon exit from background debug mode or stop mode.
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 71 5.5 interrupts interrupts provide a way to save the current cpu status and registers, execute an interrupt service routine (isr), and then restore the cpu status so processing resumes where it left off before the interrupt. other than the software interrupt (swi), which is a program instruction, interrupts are caused by hardware events such as an edge on the irq pin or a timer-over?w event. the debug module can also generate an swi under certain circumstances. if an event occurs in an enabled interrupt source, an associated read-only status ?g will become set. the cpu will not respond unless the local interrupt enable is a 1 to enable the interrupt and the i bit in the ccr is 0 to allow interrupts. the global interrupt mask (i bit) in the ccr is initially set after reset which prevents all maskable interrupt sources. the user program initializes the stack pointer and performs other system setup before clearing the i bit to allow the cpu to respond to interrupts. when the cpu receives a quali?d interrupt request, it completes the current instruction before responding to the interrupt. the interrupt sequence obeys the same cycle-by-cycle sequence as the swi instruction and consists of: saving the cpu registers on the stack setting the i bit in the ccr to mask further interrupts fetching the interrupt vector for the highest-priority interrupt that is currently pending filling the instruction queue with the ?st three bytes of program information starting from the address fetched from the interrupt vector locations while the cpu is responding to the interrupt, the i bit is automatically set to avoid the possibility of another interrupt interrupting the isr itself (this is called nesting of interrupts). normally, the i bit is restored to 0 when the ccr is restored from the value stacked on entry to the isr. in rare cases, the i bit can be cleared inside an isr (after clearing the status ?g that generated the interrupt) so that other interrupts can be serviced without waiting for the ?st service routine to ?ish. this practice is not recommended for anyone other than the most experienced programmers because it can lead to subtle program errors that are dif?ult to debug. the interrupt service routine ends with a return-from-interrupt (rti) instruction which restores the ccr, a, x, and pc registers to their pre-interrupt values by reading the previously saved information from the stack. note for compatibility with m68hc08 devices, the h register is not automatically saved and restored. it is good programming practice to push h onto the stack at the start of the interrupt service routine (isr) and restore it immediately before the rti that is used to return from the isr. if more than one interrupt is pending when the i bit is cleared, the highest priority source is serviced ?st (see table 5-1 ).
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 72 freescale semiconductor 5.5.1 interrupt stack frame figure 5-1 shows the contents and organization of a stack frame. before the interrupt, the stack pointer (sp) points at the next available byte location on the stack. the current values of cpu registers are stored on the stack starting with the low-order byte of the program counter (pcl) and ending with the ccr. after stacking, the sp points at the next available location on the stack which is the address that is one less than the address where the ccr was saved. the pc value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. figure 5-1. interrupt stack frame when an rti instruction is executed, these values are recovered from the stack in reverse order. as part of the rti sequence, the cpu ?ls the instruction pipeline by reading three bytes of program information, starting from the pc address recovered from the stack. the status ?g corresponding to the interrupt source must be acknowledged (cleared) before returning from the isr. typically, the ?g is cleared at the beginning of the isr so that if another interrupt is generated by this same source, it will be registered so it can be serviced after completion of the current isr. 5.5.2 external interrupt request (irq) pin external interrupts are managed by the irq status and control register, irqsc. when the irq function is enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. when the mcu is in stop mode and system clocks are shut down, a separate asynchronous path is used so the irq (if enabled) can wake the mcu. 5.5.2.1 pin con?uration options the irq pin enable (irqpe) control bit in irqsc must be 1 in order for the irq pin to act as the interrupt request (irq) input. as an irq input, the user can choose the polarity of edges or levels detected (irqedg), whether the pin detects edges-only or edges and levels (irqmod), and whether an event causes an interrupt or only sets the irqf ?g which can be polled by software. condition code register accumulator index register (low byte x) program counter high * high byte (h) of index register is not automatically stacked. * program counter low 70 unstacking order stacking order 5 4 3 2 1 1 2 3 4 5 toward lower addresses toward higher addresses sp before sp after interrupt stacking the interrupt
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 73 the irq pin, when enabled, defaults to use an internal pull device (irqpdd = 0), the device is a pull-up or pull-down depending on the polarity chosen. if the user desires to use an external pull-up or pull-down, the irqpdd can be written to a 1 to turn off the internal device. bih and bil instructions may be used to detect the level on the irq pin when the pin is con?ured to act as the irq input. 5.5.2.2 edge and level sensitivity the irqmod control bit recon?ures the detection logic so it detects edge events and pin levels. in the edge and level detection mode, the irqf status ?g becomes set when an edge is detected (when the irq pin changes from the deasserted to the asserted level), but the ?g is continuously set (and cannot be cleared) as long as the irq pin remains at the asserted level. 5.5.3 interrupt vectors, sources, and local masks table 5-1 provides a summary of all interrupt sources. higher-priority sources are located toward the bottom of the table. the high-order byte of the address for the interrupt service routine is located at the ?st address in the vector address column, and the low-order byte of the address for the interrupt service routine is located at the next higher address. when an interrupt condition occurs, an associated ?g bit becomes set. if the associated local interrupt enable is 1, an interrupt request is sent to the cpu. within the cpu, if the global interrupt mask (i bit in the ccr) is 0, the cpu will ?ish the current instruction; stack the pcl, pch, x, a, and ccr cpu registers; set the i bit; and then fetch the interrupt vector for the highest priority pending interrupt. processing then continues in the interrupt service routine.
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 74 freescale semiconductor table 5-1. vector summary 1 1 vector priority is shown from lowest (?st row) to highest (last row). for example, vreset is the highest priority vector. vector no. address (high/low) vector name module source enable description 31 0xffc0/0xffc1 vacmp2 acmp2 acf acie analog comparator 2 30 0xffc2/0xffc3 vacmp1 acmp1 acf acie analog comparator 1 29 0xffc4/0xffc5 vcantx mscan txe[2:0] txeie[2:0] can transmit 28 0xffc6/0xffc7 vcanrx mscan rxf rxfie can receive 27 0xffc8/0xffc9 vcanerr mscan cscif, ovrif cscie, ovrie can errors 26 0xffca/0xffcb vcanwu mscan wupif wupie can wake-up 25 0xffcc/0xffcd vrtc rtc rtif rtie real-time interrupt 24 0xffce/0xffcf viic iic iicis iicie iic control 23 0xffd0/0xffd1 vadc adc coco aien adc 22 0xffd2/0xffd3 vport port a,b,d ptaif, ptbif, ptdif ptaie, ptbie, ptdie port pins 21 0xffd4/0xffd5 vsci2tx sci2 tdre, tc tie, tcie sci2 transmit 20 0xffd6/0xffd7 vsci2rx sci2 idle, lbkdif, rdrf, rxedgif ilie, lbkdie, rie, rxedgie sci2 receive 19 0xffd8/0xffd9 vsci2err sci2 or, nf fe, pf orie, nfie, feie, pfie sci2 error 18 0xffda/0xffdb vsci1tx sci1 tdre, tc tie, tcie sci1 transmit 17 0xffdc/0xffdd vsci1rx sci1 idle, lbkdif, rdrf, rxedgif ilie, lbkdie, rie, rxedgie sci1 receive 16 0xffde/0xffdf vsci1err sci1 or, nf, fe, pf orie, nfie, feie, pfie sci1 error 15 0xffe0/0xffe1 vspi spi spif, modf, sptef spie, spie, sptie spi 14 0xffe2/0xffe3 vtpm2ovf tpm2 tof toie tpm2 over?w 13 0xffe4/0xffe5 vtpm2ch1 tpm2 ch1f ch1ie tpm2 channel 1 12 0xffe6/0xffe7 vtpm2ch0 tpm2 ch0f ch0ie tpm2 channel 0 11 0xffe8/0xffe9 vtpm1ovf tpm1 tof toie tpm1 over?w 10 0xffea/0xffeb vtpm1ch5 tpm1 ch5f ch5ie tpm1 channel 5 9 0xffec/0xffed vtpm1ch4 tpm1 ch4f ch4ie tpm1 channel 4 8 0xffee/0xffef vtpm1ch3 tpm1 ch3f ch3ie tpm1 channel 3 7 0xfff0/0xfff1 vtpm1ch2 tpm1 ch2f ch2ie tpm1 channel 2 6 0xfff2/0xfff3 vtpm1ch1 tpm1 ch1f ch1ie tpm1 channel 1 5 0xfff4/0xfff5 vtpm1ch0 tpm1 ch0f ch0ie tpm1 channel 0 4 0xfff6/0xfff7 vlol mcg lols lolie mcg loss of lock 3 0xfff8/0xfff9 vlvd system control lvwf lvwie low-voltage warning 2 0xfffa/0xfffb virq irq irqf irqie irq pin 1 0xfffc/0xfffd vswi core swi instruction software interrupt 0 0xfffe/0xffff vreset system control cop, loc, lv d, reset, ilop, ilad, por, bdfr cope cme lvdre watchdog timer loss-of-clock low-voltage detect external pin illegal opcode illegal address power-on-reset bdm-forced reset
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 75 5.6 low-voltage detect (lvd) system the mc9s08de60 series includes a system to protect against low-voltage conditions in order to protect memory contents and control mcu system states during supply voltage variations. the system is comprised of a power-on reset (por) circuit and a lvd circuit with trip voltages for warning and detection. the lvd circuit is enabled when lvde in spmsc1 is set to 1. the lvd is disabled upon entering any of the stop modes unless lvdse is set in spmsc1. if lvdse and lvde are both set, then the mcu cannot enter stop2 (it will enter stop3 instead), and the current consumption in stop3 with the lvd enabled will be higher. 5.6.1 power-on reset operation when power is initially applied to the mcu, or when the supply voltage drops below the power-on reset rearm voltage level, v por , the por circuit will cause a reset condition. as the supply voltage rises, the lvd circuit will hold the mcu in reset until the supply has risen above the low-voltage detection low threshold, v lvdl . both the por bit and the lvd bit in srs are set following a por. 5.6.2 low-voltage detection (lvd) reset operation the lvd can be con?ured to generate a reset upon detection of a low-voltage condition by setting lvdre to 1. the low-voltage detection threshold is determined by the lvdv bit. after an lvd reset has occurred, the lvd system will hold the mcu in reset until the supply voltage has risen above the low-voltage detection threshold. the lvd bit in the srs register is set following either an lvd reset or por. 5.6.3 low-voltage warning (lvw) interrupt operation the lvd system has a low-voltage warning ?g to indicate to the user that the supply voltage is approaching the low-voltage condition. when a low-voltage warning condition is detected and is con?ured for interrupt operation (lvwie set to 1), lvwf in spmsc1 will be set and an lvw interrupt request will occur. 5.7 mclk output the pta0 pin is shared with the mclk clock output. if the mcsel bits are all zeroes, the mclk clock is disabled. setting any of the mcsel bits causes the pta0 pin to output a divided version of the internal mcu bus clock regardless of the state of the port data direction control bit for the pin. the divide ratio is determined by the mcsel bits. the slew rate and drive strength for the pin are controlled by ptase0 and ptads0, respectively. the maximum clock output frequency is limited if slew rate control is enabled, see the electrical speci?ations for the maximum frequency under different conditions.
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 76 freescale semiconductor 5.8 reset, interrupt, and system control registers and control bits one 8-bit register in the direct page register space and eight 8-bit registers in the high-page register space are related to reset and interrupt systems. refer to table 4-2 and table 4-3 in chapter 4, ?emory ,?of this data sheet for the absolute address assignments for all registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. some control bits in the sopt1 and spmsc2 registers are related to modes of operation. although brief descriptions of these bits are provided here, the related functions are discussed in greater detail in chapter 3, ?odes of operation .
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 77 5.8.1 interrupt pin request status and control register (irqsc) this direct page register includes status and control bits which are used to con?ure the irq function, report status, and acknowledge irq events. 76543210 r0 irqpdd irqedg irqpe irqf 0 irqie irqmod w irqack reset 00000000 = unimplemented or reserved figure 5-2. interrupt request status and control register (irqsc) table 5-2. irqsc register field descriptions field description 6 irqpdd interrupt request (irq) pull device disable ?this read/write control bit is used to disable the internal pull-up/pull-down device when the irq pin is enabled (irqpe = 1) allowing for an external device to be used. 0 irq pull device enabled if irqpe = 1. 1 irq pull device disabled if irqpe = 1. 5 irqedg interrupt request (irq) edge select ?this read/write control bit is used to select the polarity of edges or levels on the irq pin that cause irqf to be set. the irqmod control bit determines whether the irq pin is sensitive to both edges and levels or only edges. when the irq pin is enabled as the irq input and is con?ured to detect rising edges, it has a pull-down. when the irq pin is enabled as the irq input and is con?ured to detect falling edges, it has a pull-up. 0 irq is falling edge or falling edge/low-level sensitive. 1 irq is rising edge or rising edge/high-level sensitive. 4 irqpe irq pin enable this read/write control bit enables the irq pin function. when this bit is set the irq pin can be used as an interrupt request. 0 irq pin function is disabled. 1 irq pin function is enabled. 3 irqf irq flag ?this read-only status bit indicates when an interrupt request event has occurred. 0 no irq request. 1 irq event detected. 2 irqack irq acknowledge this write-only bit is used to acknowledge interrupt request events (write 1 to clear irqf). writing 0 has no meaning or effect. reads always return 0. if edge-and-level detection is selected (irqmod = 1), irqf cannot be cleared while the irq pin remains at its asserted level. 1 irqie irq interrupt enable ?this read/write control bit determines whether irq events generate an interrupt request. 0 interrupt request when irqf set is disabled (use polling). 1 interrupt requested whenever irqf = 1. 0 irqmod irq detection mode ?this read/write control bit selects either edge-only detection or edge-and-level detection. the irqedg control bit determines the polarity of edges and levels that are detected as interrupt request events. see section 5.5.2.2, ?dge and level sensitivity ?for more details. 0 irq event on falling edges or rising edges only. 1 irq event on falling edges and low levels or on rising edges and high levels.
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 78 freescale semiconductor 5.8.2 system reset status register (srs) this high page register includes read-only status ?gs to indicate the source of the most recent reset. when a debug host forces reset by writing 1 to bdfr in the sbdfr register, none of the status bits in srs will be set. writing any value to this register address causes a cop reset when the cop is enabled except the values 0x55 and 0xaa. writing a 0x55-0xaa sequence to this address clears the cop watchdog timer without affecting the contents of this register. the reset state of these bits depends on what caused the mcu to reset. figure 5-3. system reset status (srs) 76543210 r por pin cop ilop ilad loc lvd 0 w writing 0x55, 0xaa to srs address clears cop watchdog timer. por: 10000010 lvd: u0000010 any other reset: 0 note (1) 1 any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits corresponding to sources that are not active at the time of reset entry will be cleared. note (1) note (1) note (1) 000 table 5-3. srs register field descriptions field description 7 por power-on reset reset was caused by the power-on detection logic. because the internal supply voltage was ramping up at the time, the low-voltage reset (lvd) status bit is also set to indicate that the reset occurred while the internal supply was below the lvd threshold. 0 reset not caused by por. 1 por caused reset. 6 pin external reset pin ?reset was caused by an active-low level on the external reset pin. 0 reset not caused by external reset pin. 1 reset came from external reset pin. 5 cop computer operating properly (cop) watchdog reset was caused by the cop watchdog timer timing out. this reset source can be blocked by cope = 0. 0 reset not caused by cop timeout. 1 reset caused by cop timeout. 4 ilop illegal opcode reset was caused by an attempt to execute an unimplemented or illegal opcode. the stop instruction is considered illegal if stop is disabled by stope = 0 in the sopt register. the bgnd instruction is considered illegal if active background mode is disabled by enbdm = 0 in the bdcsc register. 0 reset not caused by an illegal opcode. 1 reset caused by an illegal opcode. 3 ilad illegal address reset was caused by an attempt to access either data or an instruction at an unimplemented memory address. 0 reset not caused by an illegal address. 1 reset caused by an illegal address.
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 79 5.8.3 system background debug force reset register (sbdfr) this high page register contains a single write-only control bit. a serial background command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return 0x00. figure 5-4. system background debug force reset register (sbdfr) 2 loc loss of clock ?reset was caused by a loss of external clock. 0 reset not caused by loss of external clock 1 reset caused by loss of external clock 1 lv d low-voltage detect if the lvdre bit is set and the supply drops below the lvd trip voltage, an lvd reset will occur. this bit is also set by por. 0 reset not caused by lvd trip or por. 1 reset caused by lvd trip or por. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background debug commands, not from user programs. reset: 00000000 = unimplemented or reserved table 5-4. sbdfr register field descriptions field description 0 bdfr background debug force reset a serial background command such as write_byte can be used to allow an external debug host to force a target system reset. writing 1 to this bit forces an mcu reset. this bit cannot be written from a user program. table 5-3. srs register field descriptions field description
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 80 freescale semiconductor 5.8.4 system options register 1 (sopt1) this high page register is a write-once register so only the ?st write after reset is honored. it can be read at any time. any subsequent attempt to write to sopt1 (intentionally or unintentionally) is ignored to avoid accidental changes to these sensitive settings. this register should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. 76543210 r copt stope sci2ps iicps 000 w reset: 11000000 = unimplemented or reserved figure 5-5. system options register 1 (sopt1) table 5-5. sopt1 register field descriptions field description 7:6 copt[1:0] cop watchdog timeout ?these write-once bits select the timeout period of the cop. copt along with copclks in sopt2 de?es the cop timeout period. see table 5-6 . 5 stope stop mode enable ?this write-once bit is used to enable stop mode. if stop mode is disabled and a user program attempts to execute a stop instruction, an illegal opcode reset is forced. 0 stop mode disabled. 1 stop mode enabled. 4 sci2ps sci2 pin select ?this write-once bit selects the location of the rxd2 and txd2 pins of the sci2 module. 0 txd2 on ptf0, rxd2 on ptf1. 1 txd2 on pte6, rxd2 on pte7. 3 iicps iic pin select ?this write-once bit selects the location of the scl and sda pins of the iic module. 0 scl on ptf2, sda on ptf3. 1 scl on pte4, sda on pte5. table 5-6. cop con?uration options control bits clock source cop window 1 opens (copw = 1) 1 windowed cop operation requires the user to clear the cop timer in the last 25% of the selected timeout period. this column displays the minimum number of clock counts required before the cop timer can be reset when in windowed cop mode (copw = 1). cop over?w count copclks copt[1:0] n/a 0:0 n/a n/a cop is disabled 0 0:1 1 khz n/a 2 5 cycles (32 ms 2 ) 2 values shown in milliseconds based on t lpo = 1 ms. see t lpo in the appendix section a.12.1, ?ontrol timing ,?for the tolerance of this value. 0 1:0 1 khz n/a 2 8 cycles (256 ms 1 ) 0 1:1 1 khz n/a 2 10 cycles (1.024 s 1 ) 1 0:1 bus 6144 cycles 2 13 cycles 1 1:0 bus 49,152 cycles 2 16 cycles 1 1:1 bus 196,608 cycles 2 18 cycles
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 81 5.8.5 system options register 2 (sopt2) this high page register contains bits to con?ure mcu speci? features on the mc9s08de60 series devices. 76543210 r copclks 1 1 this bit can be written only one time after reset. additional writes are ignored. copw 1 0 adhts 0 mcsel w reset: 00000000 = unimplemented or reserved figure 5-6. system options register 2 (sopt2) table 5-7. sopt2 register field descriptions field description 7 copclks cop watchdog clock select ?this write-once bit selects the clock source of the cop watchdog. see table 5-6 for details. 0 internal 1-khz clock is source to cop. 1 bus clock is source to cop. 6 copw cop window this write-once bit selects the cop operation mode. when set, the 0x55-0xaa write sequence to the srs register must occur in the last 25% of the selected period. any write to the srs register during the ?st 75% of the selected period will reset the mcu. 0 normal cop operation. 1 window cop operation. 4 adhts adc hardware trigger select ?this bit selects which hardware trigger initiates conversion for the analog to digital converter when the adc hardware trigger is enabled (adctrg is set in adcsc2 register). 0 real time counter (rtc) over?w. 1 external interrupt request (irq) pin. 2:0 mcsel mclk divide select these bits enable the mclk output on pta0 pin and select the divide ratio for the mclk output according to the formula below when the mcsel bits are not equal to all zeroes. in case that the mcsel bits are all zeroes, the mclk output is disabled. mclk frequency = bus clock frequency (2 * mcsel)
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 82 freescale semiconductor 5.8.6 system device identi?ation register (sdidh, sdidl) these high page read-only registers are included so host development systems can identify the hcs08 derivative and revision number. this allows the development software to recognize where speci? memory blocks, registers, and control bits are located in a target mcu. figure 5-7. system device identi?ation register ?high (sdidh) 76543210 r reserved id11 id10 id9 id8 w reset: 0 1 1 the revision number that is hard coded into these bits re?cts the current silicon revision level. 0 1 0 1 0 1 0000 = unimplemented or reserved table 5-8. sdidh register field descriptions field description 3:0 id[11:8] part identi?ation number mc9s08de60 series mcus are hard-coded to the value 0x00e. see also id bits in table 5-9 . 76543210 r id7 id6 id5 id4 id3 id2 id1 id0 w reset: 00001110 = unimplemented or reserved figure 5-8. system device identi?ation register ?low (sdidl) table 5-9. sdidl register field descriptions field description 7:0 id[7:0] part identi?ation number mc9s08de60 series mcus are hard-coded to the value 0x00e. see also id bits in table 5-8 .
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 83 5.8.7 system power management status and control 1 register (spmsc1) this high page register contains status and control bits to support the low-voltage detect function, and to enable the bandgap voltage reference for use by the adc and acmp modules. this register should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. figure 5-9. system power management status and control 1 register (spmsc1) 76543210 r lvwf 1 1 lvwf will be set in the case when v supply transitions below the trip point or after reset and v supply is already below v lv w . 0 lvwie lvdre 2 2 this bit can be written only one time after reset. additional writes are ignored. lvdse lvde 2 0 bgbe w lv wac k reset: 00011100 = unimplemented or reserved table 5-10. spmsc1 register field descriptions field description 7 lvwf low-voltage warning flag ?the lvwf bit indicates the low-voltage warning status. 0 low-voltage warning is not present. 1 low-voltage warning is present or was present. 6 lv wac k low-voltage warning acknowledge if lvwf = 1, a low-voltage condition has occurred. to acknowledge this low-voltage warning, write 1 to lvwack, which will automatically clear lvwf to 0 if the low-voltage warning is no longer present. 5 lvwie low-voltage warning interrupt enable ?this bit enables hardware interrupt requests for lvwf. 0 hardware interrupt disabled (use polling). 1 request a hardware interrupt when lvwf = 1. 4 lvdre low-voltage detect reset enable ?this write-once bit enables lvd events to generate a hardware reset (provided lvde = 1). 0 lvd events do not generate hardware resets. 1 force an mcu reset when an enabled low-voltage detect event occurs. 3 lvdse low-voltage detect stop enable provided lvde = 1, this read/write bit determines whether the low-voltage detect function operates when the mcu is in stop mode. 0 low-voltage detect disabled during stop mode. 1 low-voltage detect enabled during stop mode. 2 lvde low-voltage detect enable this write-once bit enables low-voltage detect logic and quali?s the operation of other bits in this register. 0 lvd logic disabled. 1 lvd logic enabled. 0 bgbe bandgap buffer enable this bit enables an internal buffer for the bandgap voltage reference for use by the adc and acmp modules on one of its internal channels. 0 bandgap buffer disabled. 1 bandgap buffer enabled.
chapter 5 resets, interrupts, and general system control mc9s08de60 series data sheet, rev. 3 84 freescale semiconductor 5.8.8 system power management status and control 2 register (spmsc2) this register is used to report the status of the low-voltage warning function, and to con?ure the stop mode behavior of the mcu. this register should be written during the users reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. figure 5-10. system power management status and control 2 register (spmsc2) 76543 210 r0 0 lv dv 1 1 this bit can be written only one time after power-on reset. additional writes are ignored. lvwv ppdf 0 0 ppdc 2 2 this bit can be written only one time after reset. additional writes are ignored. w ppdack power-on reset: 0 0 0 0 0 0 0 0 lvd reset: 0 0 u u 0 0 0 0 any other reset: 0 0 u u 0 0 0 0 = unimplemented or reserved u = unaffected by reset table 5-11. spmsc2 register field descriptions field description 5 lv dv low-voltage detect voltage select this write-once bit selects the low-voltage detect (lvd) trip point setting. it also selects the warning voltage range. see table 5-12 . 4 lvwv low-voltage warning voltage select this bit selects the low-voltage warning (lvw) trip point voltage. see table 5-12 . 3 ppdf partial power down flag ?this read-only status bit indicates that the mcu has recovered from stop2 mode. 0 mcu has not recovered from stop2 mode. 1 mcu recovered from stop2 mode. 2 ppdack partial power down acknowledge ?writing a 1 to ppdack clears the ppdf bit. 0 ppdc partial power down control ?this write-once bit controls whether stop2 or stop3 mode is selected. 0 stop3 mode enabled. 1 stop2, partial power down, mode enabled. table 5-12. lvd and lvw trip point typical values 1 1 see electrical characteristics appendix for minimum and maximum values. lvdv:lvwv lvw trip point lvd trip point 0:0 v lvw0 = 2.74 v v lvd0 = 2.56 v 0:1 v lvw1 = 2.92 v 1:0 v lvw2 = 4.3 v v lvd1 = 4.0 v 1:1 v lvw3 = 4.6 v
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 85 chapter 6 parallel input/output control this section explains software controls related to parallel input/output (i/o) and pin control. the mc9s08de60 series has seven parallel i/o ports which include a total of up to 53 i/o pins and one input-only pin. see chapter 2, ?ins and connections ,?for more information about pin assignments and external hardware considerations of these pins. many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or pin interrupts as shown in table 2-1 . the peripheral modules have priority over the general-purpose i/o functions so that when a peripheral is enabled, the i/o functions associated with the shared pins are disabled. after reset, the shared peripheral functions are disabled and the pins are con?ured as inputs (ptxddn = 0). the pin control functions for each pin are con?ured as follows: slew rate control enabled (ptxsen = 1), low drive strength selected (ptxdsn = 0), and internal pull-ups disabled (ptxpen = 0). note not all general-purpose i/o pins are available on all packages. to avoid extra current drain from ?ating input pins, the users reset initialization routine in the application program must either enable on-chip pull-up devices or change the direction of unconnected pins to outputs so the pins do not ?at. the pte1 pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up pte1 pin may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled all the way to v dd . 6.1 port data and data direction reading and writing of parallel i/os are performed through the port data registers. the direction, either input or output, is controlled through the port data direction registers. the parallel i/o port function for an individual pin is illustrated in the block diagram shown in figure 6-1 . the data direction control bit (ptxddn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. the input buffer for the associated pin is always enabled unless the pin is enabled as an analog function or is an output-only pin. when a shared digital function is enabled for a pin, the output buffer is controlled by the shared function. however, the data direction register bit will continue to control the source for reads of the port data register. when a shared analog function is enabled for a pin, both the input and output buffers are disabled. a value of 0 is read for any port data bit where the bit is an input (ptxddn = 0) and the input buffer is disabled.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 86 freescale semiconductor in general, whenever a pin is shared with both an alternate digital function and an analog function, the analog function has priority such that if both the digital and analog functions are enabled, the analog function controls the pin. it is a good programming practice to write to the port data register before changing the direction of a port pin to become an output. this ensures that the pin will not be driven momentarily with an old data value that happened to be in the port data register. figure 6-1. parallel i/o block diagram 6.2 pull-up, slew rate, and drive strength associated with the parallel i/o ports is a set of registers located in the high page register space that operate independently of the parallel i/o registers. these registers are used to control pull-ups, slew rate, and drive strength for the pins. an internal pull-up device can be enabled for each port pin by setting the corresponding bit in the pull-up enable register (ptxpen). the pull-up device is disabled if the pin is con?ured as an output by the parallel i/o control logic or any shared peripheral function regardless of the state of the corresponding pull-up enable register bit. the pull-up device is also disabled if the pin is controlled by an analog function. slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control register (ptxsen). when enabled, slew control limits the rate at which an output can transition in order to reduce emc emissions. slew rate control has no effect on pins that are con?ured as inputs. note slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. q d q d 1 0 port read ptxddn ptxdn output enable output data input dat a synchronizer data busclk
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 87 an output pin can be selected to have high output drive strength by setting the corresponding bit in the drive strength select register (ptxdsn). when high drive is selected, a pin is capable of sourcing and sinking greater current. even though every i/o pin can be selected as high drive, the user must ensure that the total current source and sink limits for the mcu are not exceeded. drive strength selection is intended to affect the dc behavior of i/o pins. however, the ac behavior is also affected. high drive allows a pin to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load. because of this, the emc emissions may be affected by enabling pins as high drive. 6.3 pin interrupts port a, port b, and port d pins can be con?ured as external interrupt inputs and as an external means of waking the mcu from stop or wait low-power modes. the block diagram for each port interrupt logic is shown figure 6-2 . figure 6-2. port interrupt block diagram writing to the ptxpsn bits in the port interrupt pin select register (ptxps) independently enables or disables each port pin. each port can be con?ured as edge sensitive or edge and level sensitive based on the ptxmod bit in the port interrupt status and control register (ptxsc). edge sensitivity can be software programmed to be either falling or rising; the level can be either low or high. the polarity of the edge or edge and level sensitivity is selected using the ptxesn bits in the port interrupt edge select register (ptxes). synchronous logic is used to detect edges. prior to detecting an edge, enabled port inputs must be at the deasserted logic level. a falling edge is detected when an enabled port input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. a rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1 during the next cycle. 6.3.1 edge only sensitivity a valid edge on an enabled port pin will set ptxif in ptxsc. if ptxie in ptxsc is set, an interrupt request will be presented to the cpu. clearing of ptxif is accomplished by writing a 1 to ptxack in ptxsc. ptxesn dq ck clr v dd ptxmod ptxie port interrupt ff ptxack reset synchronizer ptxif stop bypass stop busclk ptxpsn 0 1 s ptxps0 0 1 s ptxes0 ptxn ptxn ptx interrupt request
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 88 freescale semiconductor 6.3.2 edge and level sensitivity a valid edge or level on an enabled port pin will set ptxif in ptxsc. if ptxie in ptxsc is set, an interrupt request will be presented to the cpu. clearing of ptxif is accomplished by writing a 1 to ptxack in ptxsc provided all enabled port inputs are at their deasserted levels. ptxif will remain set if any enabled port pin is asserted while attempting to clear by writing a 1 to ptxack. 6.3.3 pull-up/pull-down resistors the port interrupt pins can be con?ured to use an internal pull-up/pull-down resistor using the associated i/o port pull-up enable register. if an internal resistor is enabled, the ptxes register is used to select whether the resistor is a pull-up (ptxesn = 0) or a pull-down (ptxesn = 1). 6.3.4 pin interrupt initialization when an interrupt pin is ?st enabled, it is possible to get a false interrupt ?g. to prevent a false interrupt request during pin interrupt initialization, the user should do the following: 1. mask interrupts by clearing ptxie in ptxsc. 2. select the pin polarity by setting the appropriate ptxesn bits in ptxes. 3. if using internal pull-up/pull-down device, con?ure the associated pull enable bits in ptxpe. 4. enable the interrupt pins by setting the appropriate ptxpsn bits in ptxps. 5. write to ptxack in ptxsc to clear any false interrupts. 6. set ptxie in ptxsc to enable interrupts. 6.4 pin behavior in stop modes pin behavior following execution of a stop instruction depends on the stop mode that is entered. an explanation of pin behavior for the various stop modes follows: stop2 mode is a partial power-down mode, whereby i/o latches are maintained in their state as before the stop instruction was executed. cpu register status and the state of i/o registers should be saved in ram before the stop instruction is executed to place the mcu in stop2 mode. upon recovery from stop2 mode, before accessing any i/o, the user should examine the state of the ppdf bit in the spmsc2 register. if the ppdf bit is 0, i/o must be initialized as if a power on reset had occurred. if the ppdf bit is 1, peripherals may require initialization to be restored to their pre-stop condition. this can be done using data previously stored in ram if it was saved before the stop instruction was executed. the user must then write a 1 to the ppdack bit in the spmsc2 register. access to i/o is now permitted again in the user application program. in stop3 mode, all i/o is maintained because internal logic circuity stays powered up. upon recovery, normal i/o function is available to the user.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 89 6.5 parallel i/o and pin control registers this section provides information about the registers associated with the parallel i/o ports. the data and data direction registers are located in page zero of the memory map. the pull up, slew rate, drive strength, and interrupt control registers are located in the high page section of the memory map. refer to tables in chapter 4, ?emory , for the absolute address assignments for all parallel i/o and their pin control registers. this section refers to registers and control bits only by their names. a freescale semiconductor-provided equate or header ?e normally is used to translate these names into the appropriate absolute addresses.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 90 freescale semiconductor 6.5.1 port a registers port a is controlled by the registers listed below. 6.5.1.1 port a data register (ptad) 6.5.1.2 port a data direction register (ptadd) 76543210 r ptad7 ptad6 ptad5 ptad4 ptad3 ptad2 ptad1 ptad0 w reset: 00000000 figure 6-3. port a data register (ptad) table 6-1. ptad register field descriptions field description 7:0 ptad[7:0] port a data register bits ?for port a pins that are inputs, reads return the logic level on the pin. for port a pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port a pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptad to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 76543210 r ptadd7 ptadd6 ptadd5 ptadd4 ptadd3 ptadd2 ptadd1 ptadd0 w reset: 00000000 figure 6-4. port a data direction register (ptadd) table 6-2. ptadd register field descriptions field description 7:0 ptadd[7:0] data direction for port a bits these read/write bits control the direction of port a pins and what is read for ptad reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port a bit n and ptad reads return the contents of ptadn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 91 6.5.1.3 port a pull enable register (ptape) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.1.4 port a slew rate enable register (ptase) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r ptape7 ptape6 ptape5 ptape4 ptape3 ptape2 ptape1 ptape0 w reset: 00000000 figure 6-5. internal pull enable for port a register (ptape) table 6-3. ptape register field descriptions field description 7:0 ptape[7:0] internal pull enable for port a bits each of these control bits determines if the internal pull-up or pull-down device is enabled for the associated pta pin. for port a pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port a bit n. 1 internal pull-up/pull-down device enabled for port a bit n. 76543210 r ptase7 ptase6 ptase5 ptase4 ptase3 ptase2 ptase1 ptase0 w reset: 00000000 figure 6-6. slew rate enable for port a register (ptase) table 6-4. ptase register field descriptions field description 7:0 ptase[7:0] output slew rate enable for port a bits each of these control bits determines if the output slew rate control is enabled for the associated pta pin. for port a pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port a bit n. 1 output slew rate control enabled for port a bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 92 freescale semiconductor 6.5.1.5 port a drive strength selection register (ptads) 6.5.1.6 port a interrupt status and control register (ptasc) 76543210 r ptads7 ptads6 ptads5 ptads4 ptads3 ptads2 ptads1 ptads0 w reset: 00000000 figure 6-7. drive strength selection for port a register (ptads) table 6-5. ptads register field descriptions field description 7:0 ptads[7:0] output drive strength selection for port a bits ?each of these control bits selects between low and high output drive for the associated pta pin. for port a pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port a bit n. 1 high output drive strength selected for port a bit n. 76543210 r0000p t a i f0 ptaie ptamod w ptaack reset: 00000000 = unimplemented or reserved figure 6-8. port a interrupt status and control register (ptasc) table 6-6. ptasc register field descriptions field description 3 ptaif port a interrupt flag ?ptaif indicates when a port a interrupt is detected. writes have no effect on ptaif. 0 no port a interrupt detected. 1 port a interrupt detected. 2 ptaack port a interrupt acknowledge ?writing a 1 to ptaack is part of the ?g clearing mechanism. ptaack always reads as 0. 1 ptaie port a interrupt enable ?ptaie determines whether a port a interrupt is requested. 0 port a interrupt request not enabled. 1 port a interrupt request enabled. 0 ptamod port a detection mode ?ptamod (along with the ptaes bits) controls the detection mode of the port a interrupt pins. 0 port a pins detect edges only. 1 port a pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 93 6.5.1.7 port a interrupt pin select register (ptaps) 6.5.1.8 port a interrupt edge select register (ptaes) 76543210 r ptaps7 ptaps6 ptaps5 ptaps4 ptaps3 ptaps2 ptaps1 ptaps0 w reset: 00000000 figure 6-9. port a interrupt pin select register (ptaps) table 6-7. ptaps register field descriptions field description 7:0 ptaps[7:0] port a interrupt pin selects ?each of the ptapsn bits enable the corresponding port a interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r ptaes7 ptaes6 ptaes5 ptaes4 ptaes3 ptaes2 ptaes1 ptaes0 w reset: 00000000 figure 6-10. port a edge select register (ptaes) table 6-8. ptaes register field descriptions field description 7:0 ptaes[7:0] port a edge selects ?each of the ptaesn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 94 freescale semiconductor 6.5.2 port b registers port b is controlled by the registers listed below. 6.5.2.1 port b data register (ptbd) 6.5.2.2 port b data direction register (ptbdd) 76543210 r ptbd7 ptbd6 ptbd5 ptbd4 ptbd3 ptbd2 ptbd1 ptbd0 w reset: 00000000 figure 6-11. port b data register (ptbd) table 6-9. ptbd register field descriptions field description 7:0 ptbd[7:0] port b data register bits ?for port b pins that are inputs, reads return the logic level on the pin. for port b pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port b pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptbd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 76543210 r ptbdd7 ptbdd6 ptbdd5 ptbdd4 ptbdd3 ptbdd2 ptbdd1 ptbdd0 w reset: 00000000 figure 6-12. port b data direction register (ptbdd) table 6-10. ptbdd register field descriptions field description 7:0 ptbdd[7:0] data direction for port b bits these read/write bits control the direction of port b pins and what is read for ptbd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port b bit n and ptbd reads return the contents of ptbdn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 95 6.5.2.3 port b pull enable register (ptbpe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.2.4 port b slew rate enable register (ptbse) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r ptbpe7 ptbpe6 ptbpe5 ptbpe4 ptbpe3 ptbpe2 ptbpe1 ptbpe0 w reset: 00000000 figure 6-13. internal pull enable for port b register (ptbpe) table 6-11. ptbpe register field descriptions field description 7:0 ptbpe[7:0] internal pull enable for port b bits each of these control bits determines if the internal pull-up or pull-down device is enabled for the associated ptb pin. for port b pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port b bit n. 1 internal pull-up/pull-down device enabled for port b bit n. 76543210 r ptbse7 ptbse6 ptbse5 ptbse4 ptbse3 ptbse2 ptbse1 ptbse0 w reset: 00000000 figure 6-14. slew rate enable for port b register (ptbse) table 6-12. ptbse register field descriptions field description 7:0 ptbse[7:0] output slew rate enable for port b bits each of these control bits determines if the output slew rate control is enabled for the associated ptb pin. for port b pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port b bit n. 1 output slew rate control enabled for port b bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 96 freescale semiconductor 6.5.2.5 port b drive strength selection register (ptbds) 6.5.2.6 port b interrupt status and control register (ptbsc) 76543210 r ptbds7 ptbds6 ptbds5 ptbds4 ptbds3 ptbds2 ptbds1 ptbds0 w reset: 00000000 figure 6-15. drive strength selection for port b register (ptbds) table 6-13. ptbds register field descriptions field description 7:0 ptbds[7:0] output drive strength selection for port b bits ?each of these control bits selects between low and high output drive for the associated ptb pin. for port b pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port b bit n. 1 high output drive strength selected for port b bit n. 76543210 r0000 ptbif 0 ptbie ptbmod w ptback reset: 00000000 = unimplemented or reserved figure 6-16. port b interrupt status and control register (ptbsc) table 6-14. ptbsc register field descriptions field description 3 ptbif port b interrupt flag ?ptbif indicates when a port b interrupt is detected. writes have no effect on ptbif. 0 no port b interrupt detected. 1 port b interrupt detected. 2 ptback port b interrupt acknowledge ?writing a 1 to ptback is part of the ?g clearing mechanism. ptback always reads as 0. 1 ptbie port b interrupt enable ?ptbie determines whether a port b interrupt is requested. 0 port b interrupt request not enabled. 1 port b interrupt request enabled. 0 ptbmod port b detection mode ?ptbmod (along with the ptbes bits) controls the detection mode of the port b interrupt pins. 0 port b pins detect edges only. 1 port b pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 97 6.5.2.7 port b interrupt pin select register (ptbps) 6.5.2.8 port b interrupt edge select register (ptbes) 76543210 r ptbps7 ptbps6 ptbps5 ptbps4 ptbps3 ptbps2 ptbps1 ptbps0 w reset: 00000000 figure 6-17. port b interrupt pin select register (ptbps) table 6-15. ptbps register field descriptions field description 7:0 ptbps[7:0] port b interrupt pin selects ?each of the ptbpsn bits enable the corresponding port b interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r ptbes7 ptbes6 ptbes5 ptbes4 ptbes3 ptbes2 ptbes1 ptbes0 w reset: 00000000 figure 6-18. port b edge select register (ptbes) table 6-16. ptbes register field descriptions field description 7:0 ptbes[7:0] port b edge selects ?each of the ptbesn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 98 freescale semiconductor 6.5.3 port c registers port c is controlled by the registers listed below. 6.5.3.1 port c data register (ptcd) 6.5.3.2 port c data direction register (ptcdd) 76543210 r ptcd7 ptcd6 ptcd5 ptcd4 ptcd3 ptcd2 ptcd1 ptcd0 w reset: 00000000 figure 6-19. port c data register (ptcd) table 6-17. ptcd register field descriptions field description 7:0 ptcd[7:0] port c data register bits ?for port c pins that are inputs, reads return the logic level on the pin. for port c pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port c pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptcd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups disabled. 76543210 r ptcdd7 ptcdd6 ptcdd5 ptcdd4 ptcdd3 ptcdd2 ptcdd1 ptcdd0 w reset: 00000000 figure 6-20. port c data direction register (ptcdd) table 6-18. ptcdd register field descriptions field description 7:0 ptcdd[7:0] data direction for port c bits these read/write bits control the direction of port c pins and what is read for ptcd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port c bit n and ptcd reads return the contents of ptcdn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 99 6.5.3.3 port c pull enable register (ptcpe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.3.4 port c slew rate enable register (ptcse) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r ptcpe7 ptcpe6 ptcpe5 ptcpe4 ptcpe3 ptcpe2 ptcpe1 ptcpe0 w reset: 00000000 figure 6-21. internal pull enable for port c register (ptcpe) table 6-19. ptcpe register field descriptions field description 7:0 ptcpe[7:0] internal pull enable for port c bits ?each of these control bits determines if the internal pull-up device is enabled for the associated ptc pin. for port c pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up device disabled for port c bit n. 1 internal pull-up device enabled for port c bit n. 76543210 r ptcse7 ptcse6 ptcse5 ptcse4 ptcse3 ptcse2 ptcse1 ptcse0 w reset: 00000000 figure 6-22. slew rate enable for port c register (ptcse) table 6-20. ptcse register field descriptions field description 7:0 ptcse[7:0] output slew rate enable for port c bits each of these control bits determines if the output slew rate control is enabled for the associated ptc pin. for port c pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port c bit n. 1 output slew rate control enabled for port c bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 100 freescale semiconductor 6.5.3.5 port c drive strength selection register (ptcds) 76543210 r ptcds7 ptcds6 ptcds5 ptcds4 ptcds3 ptcds2 ptcds1 ptcds0 w reset: 00000000 figure 6-23. drive strength selection for port c register (ptcds) table 6-21. ptcds register field descriptions field description 7:0 ptcds[7:0] output drive strength selection for port c bits ?each of these control bits selects between low and high output drive for the associated ptc pin. for port c pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port c bit n. 1 high output drive strength selected for port c bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 101 6.5.4 port d registers port d is controlled by the registers listed below. 6.5.4.1 port d data register (ptdd) 6.5.4.2 port d data direction register (ptddd) 76543210 r ptdd7 ptdd6 ptdd5 ptdd4 ptdd3 ptdd2 ptdd1 ptdd0 w reset: 00000000 figure 6-24. port d data register (ptdd) table 6-22. ptdd register field descriptions field description 7:0 ptdd[7:0] port d data register bits ?for port d pins that are inputs, reads return the logic level on the pin. for port d pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port d pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptdd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups/pull-downs disabled. 76543210 r ptddd7 ptddd6 ptddd5 ptddd4 ptddd3 ptddd2 ptddd1 ptddd0 w reset: 00000000 figure 6-25. port d data direction register (ptddd) table 6-23. ptddd register field descriptions field description 7:0 ptddd[7:0] data direction for port d bits these read/write bits control the direction of port d pins and what is read for ptdd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port d bit n and ptdd reads return the contents of ptddn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 102 freescale semiconductor 6.5.4.3 port d pull enable register (ptdpe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.4.4 port d slew rate enable register (ptdse) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r ptdpe7 ptdpe6 ptdpe5 ptdpe4 ptdpe3 ptdpe2 ptdpe1 ptdpe0 w reset: 00000000 figure 6-26. internal pull enable for port d register (ptdpe) table 6-24. ptdpe register field descriptions field description 7:0 ptdpe[7:0] internal pull enable for port d bits each of these control bits determines if the internal pull-up or pull-down device is enabled for the associated ptd pin. for port d pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up/pull-down device disabled for port d bit n. 1 internal pull-up/pull-down device enabled for port d bit n. 76543210 r ptdse7 ptdse6 ptdse5 ptdse4 ptdse3 ptdse2 ptdse1 ptdse0 w reset: 00000000 figure 6-27. slew rate enable for port d register (ptdse) table 6-25. ptdse register field descriptions field description 7:0 ptdse[7:0] output slew rate enable for port d bits each of these control bits determines if the output slew rate control is enabled for the associated ptd pin. for port d pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port d bit n. 1 output slew rate control enabled for port d bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 103 6.5.4.5 port d drive strength selection register (ptdds) 6.5.4.6 port d interrupt status and control register (ptdsc) 76543210 r ptdds7 ptdds6 ptdds5 ptdds4 ptdds3 ptdds2 ptdds1 ptdds0 w reset: 00000000 figure 6-28. drive strength selection for port d register (ptdds) table 6-26. ptdds register field descriptions field description 7:0 ptdds[7:0] output drive strength selection for port d bits ?each of these control bits selects between low and high output drive for the associated ptd pin. for port d pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port d bit n. 1 high output drive strength selected for port d bit n. 76543210 r0000 ptdif 0 ptdie ptdmod w ptdack reset: 00000000 = unimplemented or reserved figure 6-29. port d interrupt status and control register (ptdsc) table 6-27. ptdsc register field descriptions field description 3 ptdif port d interrupt flag ?ptdif indicates when a port d interrupt is detected. writes have no effect on ptdif. 0 no port d interrupt detected. 1 port d interrupt detected. 2 ptdack port d interrupt acknowledge ?writing a 1 to ptdack is part of the ?g clearing mechanism. ptdack always reads as 0. 1 ptdie port d interrupt enable ?ptdie determines whether a port d interrupt is requested. 0 port d interrupt request not enabled. 1 port d interrupt request enabled. 0 ptdmod port a detection mode ?ptdmod (along with the ptdes bits) controls the detection mode of the port d interrupt pins. 0 port d pins detect edges only. 1 port d pins detect both edges and levels.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 104 freescale semiconductor 6.5.4.7 port d interrupt pin select register (ptdps) 6.5.4.8 port d interrupt edge select register (ptdes) 76543210 r ptdps7 ptdps6 ptdps5 ptdps4 ptdps3 ptdps2 ptdps1 ptdps0 w reset: 00000000 figure 6-30. port d interrupt pin select register (ptdps) table 6-28. ptdps register field descriptions field description 7:0 ptdps[7:0] port d interrupt pin selects ?each of the ptdpsn bits enable the corresponding port d interrupt pin. 0 pin not enabled as interrupt. 1 pin enabled as interrupt. 76543210 r ptdes7 ptdes6 ptdes5 ptdes4 ptdes3 ptdes2 ptdes1 ptdes0 w reset: 00000000 figure 6-31. port d edge select register (ptdes) table 6-29. ptdes register field descriptions field description 7:0 ptdes[7:0] port d edge selects ?each of the ptdesn bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. 0 a pull-up device is connected to the associated pin and detects falling edge/low level for interrupt generation. 1 a pull-down device is connected to the associated pin and detects rising edge/high level for interrupt generation.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 105 6.5.5 port e registers port e is controlled by the registers listed below. 6.5.5.1 port e data register (pted) 6.5.5.2 port e data direction register (ptedd) 76543210 r pted7 pted6 pted5 pted4 pted3 pted2 pted1 1 1 reads of this bit always return the pin value of the associated pin, regardless of the value stored in the port data direction bit. pted0 w reset: 00000000 figure 6-32. port e data register (pted) table 6-30. pted register field descriptions field description 7:0 pted[7:0] port e data register bits ?for port e pins that are inputs, reads return the logic level on the pin. for port e pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port e pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces pted to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups disabled. 76543210 r ptedd7 ptedd6 ptedd5 ptedd4 ptedd3 ptedd2 ptedd1 1 1 ptedd1 has no effect on the input-only pte1 pin. ptedd0 w reset: 00000000 figure 6-33. port e data direction register (ptedd) table 6-31. ptedd register field descriptions field description 7:0 ptedd[7:0] data direction for port e bits these read/write bits control the direction of port e pins and what is read for pted reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port e bit n and pted reads return the contents of ptedn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 106 freescale semiconductor 6.5.5.3 port e pull enable register (ptepe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.5.4 port e slew rate enable register (ptese) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r ptepe7 ptepe6 ptepe5 ptepe4 ptepe3 ptepe2 ptepe1 ptepe0 w reset: 00000000 figure 6-34. internal pull enable for port e register (ptepe) table 6-32. ptepe register field descriptions field description 7:0 ptepe[7:0] internal pull enable for port e bits ?each of these control bits determines if the internal pull-up device is enabled for the associated pte pin. for port e pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up device disabled for port e bit n. 1 internal pull-up device enabled for port e bit n. 76543210 r ptese7 ptese6 ptese5 ptese4 ptese3 ptese2 ptese1 1 1 ptese1 has no effect on the input-only pte1 pin. ptese0 w reset: 00000000 figure 6-35. slew rate enable for port e register (ptese) table 6-33. ptese register field descriptions field description 7:0 ptese[7:0] output slew rate enable for port e bits each of these control bits determines if the output slew rate control is enabled for the associated pte pin. for port e pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port e bit n. 1 output slew rate control enabled for port e bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 107 6.5.5.5 port e drive strength selection register (pteds) 76543210 r pteds7 pteds6 pteds5 pteds4 pteds3 pteds2 pteds1 1 1 pteds1 has no effect on the input-only pte1 pin. pteds0 w reset: 00000000 figure 6-36. drive strength selection for port e register (pteds) table 6-34. pteds register field descriptions field description 7:0 pteds[7:0] output drive strength selection for port e bits ?each of these control bits selects between low and high output drive for the associated pte pin. for port e pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port e bit n. 1 high output drive strength selected for port e bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 108 freescale semiconductor 6.5.6 port f registers port f is controlled by the registers listed below. 6.5.6.1 port f data register (ptfd) 6.5.6.2 port f data direction register (ptfdd) 76543210 r ptfd7 ptfd6 ptfd5 ptfd4 ptfd3 ptfd2 ptfd1 ptfd0 w reset: 00000000 figure 6-37. port f data register (ptfd) table 6-35. ptfd register field descriptions field description 7:0 ptfd[7:0] port f data register bits ?for port f pins that are inputs, reads return the logic level on the pin. for port f pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port f pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptfd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups disabled. 76543210 r ptfdd7 ptfdd6 ptfdd5 ptfdd4 ptfdd3 ptfdd2 ptfdd1 ptfdd0 w reset: 00000000 figure 6-38. port f data direction register (ptfdd) table 6-36. ptfdd register field descriptions field description 7:0 ptfdd[7:0] data direction for port f bits these read/write bits control the direction of port f pins and what is read for ptfd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port f bit n and ptfd reads return the contents of ptfdn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 109 6.5.6.3 port f pull enable register (ptfpe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.6.4 port f slew rate enable register (ptfse) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r ptfpe7 ptfpe6 ptfpe5 ptfpe4 ptfpe3 ptfpe2 ptfpe1 ptfpe0 w reset: 00000000 figure 6-39. internal pull enable for port f register (ptfpe) table 6-37. ptfpe register field descriptions field description 7:0 ptfpe[7:0] internal pull enable for port f bits ?each of these control bits determines if the internal pull-up device is enabled for the associated ptf pin. for port f pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up device disabled for port f bit n. 1 internal pull-up device enabled for port f bit n. 76543210 r ptfse7 ptfse6 ptfse5 ptfse4 ptfse3 ptfse2 ptfse1 ptfse0 w reset: 00000000 figure 6-40. slew rate enable for port f register (ptfse) table 6-38. ptfse register field descriptions field description 7:0 ptfse[7:0] output slew rate enable for port f bits each of these control bits determines if the output slew rate control is enabled for the associated ptf pin. for port f pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port f bit n. 1 output slew rate control enabled for port f bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 110 freescale semiconductor 6.5.6.5 port f drive strength selection register (ptfds) 76543210 r ptfds7 ptfds6 ptfds5 ptfds4 ptfds3 ptfds2 ptfds1 ptfds0 w reset: 00000000 figure 6-41. drive strength selection for port f register (ptfds) table 6-39. ptfds register field descriptions field description 7:0 ptfds[7:0] output drive strength selection for port f bits ?each of these control bits selects between low and high output drive for the associated ptf pin. for port f pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port f bit n. 1 high output drive strength selected for port f bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 111 6.5.7 port g registers port g is controlled by the registers listed below. 6.5.7.1 port g data register (ptgd) 6.5.7.2 port g data direction register (ptgdd) 76543210 r0 0 ptgd5 ptgd4 ptgd3 ptgd2 ptgd1 ptgd0 w reset: 00000000 = unimplemented or reserved figure 6-42. port g data register (ptgd) table 6-40. ptgd register field descriptions field description 5:0 ptgd[5:0] port g data register bits for port g pins that are inputs, reads return the logic level on the pin. for port g pins that are con?ured as outputs, reads return the last value written to this register. writes are latched into all bits of this register. for port g pins that are con?ured as outputs, the logic level is driven out the corresponding mcu pin. reset forces ptgd to all 0s, but these 0s are not driven out the corresponding pins because reset also con?ures all port pins as high-impedance inputs with pull-ups disabled. 76543210 r0 0 ptgdd5 ptgdd4 ptgdd3 ptgdd2 ptgdd1 ptgdd0 w reset: 00000000 = unimplemented or reserved figure 6-43. port g data direction register (ptgdd) table 6-41. ptgdd register field descriptions field description 5:0 ptgdd[5:0] data direction for port g bits these read/write bits control the direction of port g pins and what is read for ptgd reads. 0 input (output driver disabled) and reads return the pin value. 1 output driver enabled for port g bit n and ptgd reads return the contents of ptgdn.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 112 freescale semiconductor 6.5.7.3 port g pull enable register (ptgpe) note pull-down devices only apply when using pin interrupt functions, when corresponding edge select and pin select functions are con?ured. 6.5.7.4 port g slew rate enable register (ptgse) note: slew rate reset default values may differ between engineering samples and ?al production parts. always initialize slew rate control to the desired value to ensure correct operation. 76543210 r0 0 ptgpe5 ptgpe4 ptgpe3 ptgpe2 ptgpe1 ptgpe0 w reset: 00000000 = unimplemented or reserved figure 6-44. internal pull enable for port g register (ptgpe) table 6-42. ptgpe register field descriptions field description 5:0 ptgpe[5:0] internal pull enable for port g bits ?each of these control bits determines if the internal pull-up device is enabled for the associated ptg pin. for port g pins that are con?ured as outputs, these bits have no effect and the internal pull devices are disabled. 0 internal pull-up device disabled for port g bit n. 1 internal pull-up device enabled for port g bit n. 76543210 r0 0 ptgse5 ptgse4 ptgse3 ptgse2 ptgse1 ptgse0 w reset: 00000000 = unimplemented or reserved figure 6-45. slew rate enable for port g register (ptgse) table 6-43. ptgse register field descriptions field description 5:0 ptgse[5:0] output slew rate enable for port g bits each of these control bits determines if the output slew rate control is enabled for the associated ptg pin. for port g pins that are con?ured as inputs, these bits have no effect. 0 output slew rate control disabled for port g bit n. 1 output slew rate control enabled for port g bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 freescale semiconductor 113 6.5.7.5 port g drive strength selection register (ptgds) 76543210 r0 0 ptgds5 ptgds4 ptgds3 ptgds2 ptgds1 ptgds0 w reset: 00000000 = unimplemented or reserved figure 6-46. drive strength selection for port g register (ptgds) table 6-44. ptgds register field descriptions field description 5:0 ptgds[5:0 output drive strength selection for port g bits ?each of these control bits selects between low and high output drive for the associated ptg pin. for port g pins that are con?ured as inputs, these bits have no effect. 0 low output drive strength selected for port g bit n. 1 high output drive strength selected for port g bit n.
chapter 6 parallel input/output control mc9s08de60 series data sheet, rev. 3 114 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 115 chapter 7 central processor unit (s08cpuv3) 7.1 introduction this section provides summary information about the registers, addressing modes, and instruction set of the cpu of the hcs08 family. for a more detailed discussion, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1/d. the hcs08 cpu is fully source- and object-code-compatible with the m68hc08 cpu. several instructions and enhanced addressing modes were added to improve c compiler ef?iency and to support a new background debug system which replaces the monitor mode of earlier m68hc08 microcontrollers (mcu). 7.1.1 features features of the hcs08 cpu include: object code fully upward-compatible with m68hc05 and m68hc08 families all registers and memory are mapped to a single 64-kbyte address space 16-bit stack pointer (any size stack anywhere in 64-kbyte address space) 16-bit index register (h:x) with powerful indexed addressing modes 8-bit accumulator (a) many instructions treat x as a second general-purpose 8-bit register seven addressing modes: inherent ?operands in internal registers relative ?8-bit signed offset to branch destination immediate ?operand in next object code byte(s) direct ?operand in memory at 0x0000?x00ff extended ?operand anywhere in 64-kbyte address space indexed relative to h:x ?five submodes including auto increment indexed relative to sp ?improves c ef?iency dramatically memory-to-memory data move instructions with four address mode combinations over?w, half-carry, negative, zero, and carry condition codes support conditional branching on the results of signed, unsigned, and binary-coded decimal (bcd) operations ef?ient bit manipulation instructions fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions stop and wait instructions to invoke low-power operating modes
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 116 freescale semiconductor 7.2 programmers model and cpu registers figure 7-1 shows the ve cpu registers. cpu registers are not part of the memory map. figure 7-1. cpu registers 7.2.1 accumulator (a) the a accumulator is a general-purpose 8-bit register. one operand input to the arithmetic logic unit (alu) is connected to the accumulator and the alu results are often stored into the a accumulator after arithmetic and logical operations. the accumulator can be loaded from memory using various addressing modes to specify the address where the loaded data comes from, or the contents of a can be stored to memory using various addressing modes to specify the address where data from a will be stored. reset has no effect on the contents of the a accumulator. 7.2.2 index register (h:x) this 16-bit register is actually two separate 8-bit registers (h and x), which often work together as a 16-bit address pointer where h holds the upper byte of an address and x holds the lower byte of the address. all indexed addressing mode instructions use the full 16-bit value in h:x as an index reference pointer; however, for compatibility with the earlier m68hc05 family, some instructions operate only on the low-order 8-bit half (x). many instructions treat x as a second general-purpose 8-bit register that can be used to hold 8-bit data values. x can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. transfer instructions allow data to be transferred from a or transferred to a where arithmetic and logical operations can then be performed. for compatibility with the earlier m68hc05 family, h is forced to 0x00 during reset. reset has no effect on the contents of x. sp pc condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow h x 0 0 0 7 15 15 70 accumulator a index register (low) index register (high) stack pointer 87 program counter 16-bit index register h:x ccr c v11hinz
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 117 7.2.3 stack pointer (sp) this 16-bit address pointer register points at the next available location on the automatic last-in-?st-out (lifo) stack. the stack may be located anywhere in the 64-kbyte address space that has ram and can be any size up to the amount of available ram. the stack is used to automatically save the return address for subroutine calls, the return address and cpu registers during interrupts, and for local variables. the ais (add immediate to stack pointer) instruction adds an 8-bit signed immediate value to sp. this is most often used to allocate or deallocate space for local variables on the stack. sp is forced to 0x00ff at reset for compatibility with the earlier m68hc05 family. hcs08 programs normally change the value in sp to the address of the last location (highest address) in on-chip ram during reset initialization to free up direct page ram (from the end of the on-chip registers to 0x00ff). the rsp (reset stack pointer) instruction was included for compatibility with the m68hc05 family and is seldom used in new hcs08 programs because it only affects the low-order half of the stack pointer. 7.2.4 program counter (pc) the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. during normal program execution, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, interrupt, and return operations load the program counter with an address other than that of the next sequential location. this is called a change-of-?w. during reset, the program counter is loaded with the reset vector that is located at 0xfffe and 0xffff. the vector stored there is the address of the ?st instruction that will be executed after exiting the reset state. 7.2.5 condition code register (ccr) the 8-bit condition code register contains the interrupt mask (i) and ve ?gs that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to 1. the following paragraphs describe the functions of the condition code bits in general terms. for a more detailed explanation of how each instruction sets the ccr bits, refer to the hcs08 family reference manual, volume 1, freescale semiconductor document order number hcs08rmv1.
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 118 freescale semiconductor figure 7-2. condition code register table 7-1. ccr register field descriptions field description 7 v twos complement over?w flag the cpu sets the over?w ?g when a twos complement over?w occurs. the signed branch instructions bgt, bge, ble, and blt use the over?w ?g. 0 no over?w 1 over?w 4 h half-carry flag the cpu sets the half-carry ?g when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry ?g is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c condition code bits to automatically add a correction value to the result from a previous add or adc on bcd operands to correct the result to a valid bcd value. 0 no carry between bits 3 and 4 1 carry between bits 3 and 4 3 i interrupt mask bit ?when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the ?st instruction of the interrupt service routine is executed. interrupts are not recognized at the instruction boundary after any instruction that clears i (cli or tap). this ensures that the next instruction after a cli or tap will always be executed without the possibility of an intervening interrupt, provided i was set. 0 interrupts enabled 1 interrupts disabled 2 n negative flag ?the cpu sets the negative ?g when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. simply loading or storing an 8-bit or 16-bit value causes n to be set if the most signi?ant bit of the loaded or stored value was 1. 0 non-negative result 1 negative result 1 z zero flag ?the cpu sets the zero ?g when an arithmetic operation, logic operation, or data manipulation produces a result of 0x00 or 0x0000. simply loading or storing an 8-bit or 16-bit value causes z to be set if the loaded or stored value was all 0s. 0 non-zero result 1 zero result 0 c carry/borrow flag the cpu sets the carry/borrow ?g when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions such as bit test and branch, shift, and rotate ?also clear or set the carry/borrow ?g. 0 no carry out of bit 7 1 carry out of bit 7 condition code register carry zero negative interrupt mask half-carry (from bit 3) two? complement overflow 70 ccr c v11hinz
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 119 7.3 addressing modes addressing modes de?e the way the cpu accesses operands and data. in the hcs08, all memory, status and control registers, and input/output (i/o) ports share a single 64-kbyte linear address space so a 16-bit binary address can uniquely identify any memory location. this arrangement means that the same instructions that access variables in ram can also be used to access i/o and control registers or nonvolatile program space. some instructions use more than one addressing mode. for instance, move instructions use one addressing mode to specify the source operand and a second addressing mode to specify the destination address. instructions such as brclr, brset, cbeq, and dbnz use one addressing mode to specify the location of an operand for a test and then use relative addressing mode to specify the branch destination address when the tested condition is true. for brclr, brset, cbeq, and dbnz, the addressing mode listed in the instruction set tables is the addressing mode needed to access the operand to be tested, and relative addressing mode is implied for the branch destination. 7.3.1 inherent addressing mode (inh) in this addressing mode, operands needed to complete the instruction (if any) are located within cpu registers so the cpu does not need to access memory to get any operands. 7.3.2 relative addressing mode (rel) relative addressing mode is used to specify the destination location for branch instructions. a signed 8-bit offset value is located in the memory location immediately following the opcode. during execution, if the branch condition is true, the signed offset is sign-extended to a 16-bit value and is added to the current contents of the program counter, which causes program execution to continue at the branch destination address. 7.3.3 immediate addressing mode (imm) in immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. in the case of a 16-bit immediate operand, the high-order byte is located in the next memory location after the opcode, and the low-order byte is located in the next memory location after that. 7.3.4 direct addressing mode (dir) in direct addressing mode, the instruction includes the low-order eight bits of an address in the direct page (0x0000?x00ff). during execution a 16-bit address is formed by concatenating an implied 0x00 for the high-order half of the address and the direct address from the instruction to get the 16-bit address where the desired operand is located. this is faster and more memory ef?ient than specifying a complete 16-bit address for the operand.
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 120 freescale semiconductor 7.3.5 extended addressing mode (ext) in extended addressing mode, the full 16-bit address of the operand is located in the next two bytes of program memory after the opcode (high byte ?st). 7.3.6 indexed addressing mode indexed addressing mode has seven variations including ve that use the 16-bit h:x index register pair and two that use the stack pointer as the base reference. 7.3.6.1 indexed, no offset (ix) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. 7.3.6.2 indexed, no offset with post increment (ix+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is only used for mov and cbeq instructions. 7.3.6.3 indexed, 8-bit offset (ix1) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.4 indexed, 8-bit offset with post increment (ix1+) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. the index register pair is then incremented (h:x = h:x + 0x0001) after the operand has been fetched. this addressing mode is used only for the cbeq instruction. 7.3.6.5 indexed, 16-bit offset (ix2) this variation of indexed addressing uses the 16-bit value in the h:x index register pair plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.3.6.6 sp-relative, 8-bit offset (sp1) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction.
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 121 7.3.6.7 sp-relative, 16-bit offset (sp2) this variation of indexed addressing uses the 16-bit value in the stack pointer (sp) plus a 16-bit offset included in the instruction as the address of the operand needed to complete the instruction. 7.4 special operations the cpu performs a few special operations that are similar to instructions but do not have opcodes like other cpu instructions. in addition, a few instructions such as stop and wait directly affect other mcu circuitry. this section provides additional information about these operations. 7.4.1 reset sequence reset can be caused by a power-on-reset (por) event, internal conditions such as the cop (computer operating properly) watchdog, or by assertion of an external active-low reset pin. when a reset event occurs, the cpu immediately stops whatever it is doing (the mcu does not wait for an instruction boundary before responding to a reset event). for a more detailed discussion about how the mcu recognizes resets and determines the source, refer to the resets, interrupts, and system con?uration chapter. the reset event is considered concluded when the sequence to determine whether the reset came from an internal source is done and when the reset pin is no longer asserted. at the conclusion of a reset event, the cpu performs a 6-cycle sequence to fetch the reset vector from 0xfffe and 0xffff and to ?l the instruction queue in preparation for execution of the ?st program instruction. 7.4.2 interrupt sequence when an interrupt is requested, the cpu completes the current instruction before responding to the interrupt. at this point, the program counter is pointing at the start of the next instruction, which is where the cpu should return after servicing the interrupt. the cpu responds to an interrupt by performing the same sequence of operations as for a software interrupt (swi) instruction, except the address used for the vector fetch is determined by the highest priority interrupt that is pending when the interrupt sequence started. the cpu sequence for an interrupt is: 1. store the contents of pcl, pch, x, a, and ccr on the stack, in that order. 2. set the i bit in the ccr. 3. fetch the high-order half of the interrupt vector. 4. fetch the low-order half of the interrupt vector. 5. delay for one free bus cycle. 6. fetch three bytes of program information starting at the address indicated by the interrupt vector to ?l the instruction queue in preparation for execution of the ?st instruction in the interrupt service routine. after the ccr contents are pushed onto the stack, the i bit in the ccr is set to prevent other interrupts while in the interrupt service routine. although it is possible to clear the i bit with an instruction in the
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 122 freescale semiconductor interrupt service routine, this would allow nesting of interrupts (which is not recommended because it leads to programs that are dif?ult to debug and maintain). for compatibility with the earlier m68hc05 mcus, the high-order half of the h:x index register pair (h) is not saved on the stack as part of the interrupt sequence. the user must use a pshh instruction at the beginning of the service routine to save h and then use a pulh instruction just before the rti that ends the interrupt service routine. it is not necessary to save h if you are certain that the interrupt service routine does not use any instructions or auto-increment addressing modes that might change the value of h. the software interrupt (swi) instruction is like a hardware interrupt except that it is not masked by the global i bit in the ccr and it is associated with an instruction opcode within the program so it is not asynchronous to program execution. 7.4.3 wait mode operation the wait instruction enables interrupts by clearing the i bit in the ccr. it then halts the clocks to the cpu to reduce overall power consumption while the cpu is waiting for the interrupt or reset event that will wake the cpu from wait mode. when an interrupt or reset event occurs, the cpu clocks will resume and the interrupt or reset event will be processed normally. if a serial background command is issued to the mcu through the background debug interface while the cpu is in wait mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in wait mode. 7.4.4 stop mode operation usually, all system clocks, including the crystal oscillator (when used), are halted during stop mode to minimize power consumption. in such systems, external circuitry is needed to control the time spent in stop mode and to issue a signal to wake up the target mcu when it is time to resume processing. unlike the earlier m68hc05 and m68hc08 mcus, the hcs08 can be con?ured to keep a minimum set of clocks running in stop mode. this optionally allows an internal periodic signal to wake the target mcu from stop mode. when a host debug system is connected to the background debug pin (bkgd) and the enbdm control bit has been set by a serial command through the background interface (or because the mcu was reset into active background mode), the oscillator is forced to remain active when the mcu enters stop mode. in this case, if a serial background command is issued to the mcu through the background debug interface while the cpu is in stop mode, cpu clocks will resume and the cpu will enter active background mode where other serial background commands can be processed. this ensures that a host development system can still gain access to a target mcu even if it is in stop mode. recovery from stop mode depends on the particular hcs08 and whether the oscillator was stopped in stop mode. refer to the modes of operation chapter for more details.
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 123 7.4.5 bgnd instruction the bgnd instruction is new to the hcs08 compared to the m68hc08. bgnd would not be used in normal user programs because it forces the cpu to stop processing user instructions and enter the active background mode. the only way to resume execution of the user program is through reset or by a host debug system issuing a go, trace1, or taggo serial command through the background debug interface. software-based breakpoints can be set by replacing an opcode at the desired breakpoint address with the bgnd opcode. when the program reaches this breakpoint address, the cpu is forced to active background mode rather than continuing the user program.
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 124 freescale semiconductor 7.5 hcs08 instruction set summary table 7-2 provides a summary of the hcs08 instruction set in all possible addressing modes. the table shows operand construction, execution time in internal bus clock cycles, and cycle-by-cycle details for each addressing mode variation of each instruction. table 7-2. instruction set summary (sheet 1 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c adc # opr8i adc opr8a adc opr16a adc oprx16 ,x adc oprx8,x adc ,x adc oprx16 ,sp adc oprx8,sp add with carry a (a) + (m) + (c) imm dir ext ix2 ix1 ix sp2 sp1 a9 b9 c9 d9 e9 f9 9e d9 9e e9 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? ? add # opr8i add opr8a add opr16a add oprx16 ,x add oprx8,x add ,x add oprx16 ,sp add oprx8,sp add without carry a (a) + (m) imm dir ext ix2 ix1 ix sp2 sp1 ab bb cb db eb fb 9e db 9e eb ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? ? ais # opr8i add immediate value (signed) to stack pointer sp (sp) + (m) imm a7 ii 2 pp ?1 aix # opr8i add immediate value (signed) to index register (h:x) h:x (h:x) + (m) imm af ii 2 pp ?1 and # opr8i and opr8a and opr16a and oprx16 ,x and oprx8 ,x and ,x and oprx16 ,sp and oprx8,sp logical and a (a) & (m) imm dir ext ix2 ix1 ix sp2 sp1 a4 b4 c4 d4 e4 f4 9e d4 9e e4 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ? ? asl opr8a asla aslx asl oprx8,x asl ,x asl oprx8,sp arithmetic shift left (same as lsl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ? 11 ? ? ? asr opr8a asra asrx asr oprx8,x asr ,x asr oprx8,sp arithmetic shift right dir inh inh ix1 ix sp1 37 47 57 67 77 9e 67 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ? 11 ? ? ? c b0 b7 0 b0 b7 c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 125 bcc rel branch if carry bit clear (if c = 0) rel 24 rr 3 ppp ?1 bclr n , opr8a clear bit n in memory (mn 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ?1 bcs rel branch if carry bit set (if c = 1) (same as blo) rel 25 rr 3 ppp ?1 beq rel branch if equal (if z = 1) rel 27 rr 3 ppp ?1 bge rel branch if greater than or equal to (if n v = 0) (signed) rel 90 rr 3 ppp ?1 bgnd enter active background if enbdm=1 waits for and processes bdm commands until go, trace1, or taggo inh 82 5+ fp...ppp ?1 bgt rel branch if greater than (if z | (n v) = 0) (signed) rel 92 rr 3 ppp ?1 bhcc rel branch if half carry bit clear (if h = 0) rel 28 rr 3 ppp ?1 bhcs rel branch if half carry bit set (if h = 1) rel 29 rr 3 ppp ?1 bhi rel branch if higher (if c | z = 0) rel 22 rr 3 ppp ?1 bhs rel branch if higher or same (if c = 0) (same as bcc) rel 24 rr 3 ppp ?1 bih rel branch if irq pin high (if irq pin = 1) rel 2f rr 3 ppp ?1 bil rel branch if irq pin low (if irq pin = 0) rel 2e rr 3 ppp ?1 bit # opr8i bit opr8a bit opr16a bit oprx16 ,x bit oprx8,x bit ,x bit oprx16 ,sp bit oprx8,sp bit test (a) & (m) (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a5 b5 c5 d5 e5 f5 9e d5 9e e5 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ble rel branch if less than or equal to (if z | (n v) = 1) (signed) rel 93 rr 3 ppp ?1 blo rel branch if lower (if c = 1) (same as bcs) rel 25 rr 3 ppp ?1 bls rel branch if lower or same (if c | z = 1) rel 23 rr 3 ppp ?1 blt rel branch if less than (if n v = 1) (signed) rel 91 rr 3 ppp ?1 bmc rel branch if interrupt mask clear (if i = 0) rel 2c rr 3 ppp ?1 bmi rel branch if minus (if n = 1) rel 2b rr 3 ppp ?1 bms rel branch if interrupt mask set (if i = 1) rel 2d rr 3 ppp ?1 bne rel branch if not equal (if z = 0) rel 26 rr 3 ppp ?1 table 7-2. instruction set summary (sheet 2 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 126 freescale semiconductor bpl rel branch if plus (if n = 0) rel 2a rr 3 ppp ?1 bra rel branch always (if i = 1) rel 20 rr 3 ppp ?1 brclr n,opr8a,rel branch if bit n in memory clear (if (mn) = 0) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ?1 ? brn rel branch never (if i = 0) rel 21 rr 3 ppp ?1 brset n,opr8a,rel branch if bit n in memory set (if (mn) = 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 rpppp rpppp rpppp rpppp rpppp rpppp rpppp rpppp ?1 ? bset n , opr8a set bit n in memory (mn 1) dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp rfwpp ?1 bsr rel branch to subroutine pc (pc) + $0002 push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 pc (pc) + rel rel ad rr 5 ssppp ?1 cbeq opr8a, rel cbeqa # opr8i,rel cbeqx # opr8i,rel cbeq oprx8,x+,rel cbeq ,x+, rel cbeq oprx8 ,sp,rel compare and... branch if (a) = (m) branch if (a) = (m) branch if (x) = (m) branch if (a) = (m) branch if (a) = (m) branch if (a) = (m) dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e 61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 5 6 rpppp pppp pppp rpppp rfppp prpppp ?1 clc clear carry bit (c 0) inh 98 1 p ?1 ? cli clear interrupt mask bit (i 0) inh 9a 1 p ?1 0 clr opr8a clra clrx clrh clr oprx8,x clr ,x clr oprx8,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e 6f dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 011 ?1 table 7-2. instruction set summary (sheet 3 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 127 cmp # opr8i cmp opr8a cmp opr16a cmp oprx16 ,x cmp oprx8 ,x cmp ,x cmp oprx16 ,sp cmp oprx8,sp compare accumulator with memory a ?m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a1 b1 c1 d1 e1 f1 9e d1 9e e1 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? com opr8a coma comx com oprx8,x com ,x com oprx8,sp complement m ( m)= $ff ?(m) (one? complement) a ( a) = $ff ?(a) x ( x) = $ff ?(x) m ( m) = $ff ?(m) m ( m) = $ff ?(m) m ( m) = $ff ?(m) dir inh inh ix1 ix sp1 33 43 53 63 73 9e 63 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 011 ? ? 1 cphx opr16a cphx #opr16i cphx opr8a cphx oprx8 ,sp compare index register (h:x) with memory (h:x) ?(m:m + $0001) (ccr updated but operands not changed) ext imm dir sp1 3e 65 75 9e f3 hh ll jj kk dd ff 6 3 5 6 prrfpp ppp rrfpp prrfpp ? 11 ? ? ? cpx # opr8i cpx opr8a cpx opr16a cpx oprx16 ,x cpx oprx8,x cpx ,x cpx oprx16 ,sp cpx oprx8,sp compare x (index register low) with memory x ?m (ccr updated but operands not changed) imm dir ext ix2 ix1 ix sp2 sp1 a3 b3 c3 d3 e3 f3 9e d3 9e e3 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? daa decimal adjust accumulator after add or adc of bcd values inh 72 1 p u11 ? ? ? dbnz opr8a , rel dbnza rel dbnzx rel dbnz oprx8 ,x, rel dbnz ,x, rel dbnz oprx8 ,sp,rel decrement a, x, or m and branch if not zero (if (result) 0) dbnzx affects x not h dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e 6b dd rr rr rr ff rr rr ff rr 7 4 4 7 6 8 rfwpppp fppp fppp rfwpppp rfwppp prfwpppp ?1 dec opr8a deca decx dec oprx8,x dec ,x dec oprx8,sp decrement m (m) ?$01 a (a) ?$01 x (x) ?$01 m (m) ?$01 m (m) ?$01 m (m) ?$01 dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e 6a dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp ? 11 ? ? div divide a (h:a) (x); h remainder inh 52 6 fffffp ?1 ? ? eor # opr8i eor opr8a eor opr16a eor oprx16 ,x eor oprx8 ,x eor ,x eor oprx16 ,sp eor oprx8,sp exclusive or memory with accumulator a (a m) imm dir ext ix2 ix1 ix sp2 sp1 a8 b8 c8 d8 e8 f8 9e d8 9e e8 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ? ? table 7-2. instruction set summary (sheet 4 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 128 freescale semiconductor inc opr8a inca incx inc oprx8 ,x inc ,x inc oprx8 ,sp increment m (m) + $01 a (a) + $01 x (x) + $01 m (m) + $01 m (m) + $01 m (m) + $01 dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e 6c dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 jmp opr8a jmp opr16a jmp oprx16,x jmp oprx8,x jmp ,x jump pc jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 3 4 4 3 3 ppp pppp pppp ppp ppp ?1 jsr opr8a jsr opr16a jsr oprx16,x jsr oprx8,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 pc unconditional address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 6 5 5 ssppp pssppp pssppp ssppp ssppp ?1 lda #opr8i lda opr8a lda opr16a lda oprx16,x lda oprx8,x lda ,x lda oprx16,sp lda oprx8,sp load accumulator from memory a (m) imm dir ext ix2 ix1 ix sp2 sp1 a6 b6 c6 d6 e6 f6 9e d6 9e e6 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 ldhx # opr16i ldhx opr8a ldhx opr16a ldhx ,x ldhx oprx16 ,x ldhx oprx8 ,x ldhx oprx8,sp load index register (h:x) h:x ( m:m + $0001) imm dir ext ix ix2 ix1 sp1 45 55 32 9e ae 9e be 9e ce 9e fe jj kk dd hh ll ee ff ff ff 3 4 5 5 6 5 5 ppp rrpp prrpp prrfp pprrpp prrpp prrpp 011 ldx # opr8i ldx opr8a ldx opr16a ldx oprx16,x ldx oprx8,x ldx ,x ldx oprx16,sp ldx oprx8,sp load x (index register low) from memory x (m) imm dir ext ix2 ix1 ix sp2 sp1 ae be ce de ee fe 9e de 9e ee ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 lsl opr8a lsla lslx lsl oprx8,x lsl ,x lsl oprx8,sp logical shift left (same as asl) dir inh inh ix1 ix sp1 38 48 58 68 78 9e 68 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 lsr opr8a lsra lsrx lsr oprx8,x lsr ,x lsr oprx8,sp logical shift right dir inh inh ix1 ix sp1 34 44 54 64 74 9e 64 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ? table 7-2. instruction set summary (sheet 5 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c c b0 b7 0 b0 b7 c 0
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 129 mov opr8a , opr8a mov opr8a,x+ mov # opr8i ,opr8a mov ,x+, opr8a move (m) destination (m) source in ix+/dir and dir/ix+ modes, h:x (h:x) + $0001 dir/dir dir/ix+ imm/dir ix+/dir 4e 5e 6e 7e dd dd dd ii dd dd 5 5 4 5 rpwpp rfwpp pwpp rfwpp 011 mul unsigned multiply x:a (x) (a) inh 42 5 ffffp ?10 ? neg opr8a nega negx neg oprx8 ,x neg ,x neg oprx8 ,sp negate m ?(m) = $00 ?(m) (two? complement) a ?(a) = $00 ?(a) x ?(x) = $00 ?(x) m ?(m) = $00 ?(m) m ?(m) = $00 ?(m) m ?(m) = $00 ?(m) dir inh inh ix1 ix sp1 30 40 50 60 70 9e 60 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 nop no operation ?uses 1 bus cycle inh 9d 1 p ?1 nsa nibble swap accumulator a (a[3:0]:a[7:4]) inh 62 1 p ?1 ora # opr8i ora opr8a ora opr16a ora oprx16 ,x ora oprx8 ,x ora ,x ora oprx16 ,sp ora oprx8,sp inclusive or accumulator and memory a (a) | (m) imm dir ext ix2 ix1 ix sp2 sp1 aa ba ca da ea fa 9e da 9e ea ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 011 psha push accumulator onto stack push (a); sp (sp) ?$0001 inh 87 2 sp ?1 pshh push h (index register high) onto stack push (h); sp (sp) ?$0001 inh 8b 2 sp ?1 pshx push x (index register low) onto stack push (x); sp (sp) ?$0001 inh 89 2 sp ?1 pula pull accumulator from stack sp (sp + $0001); pull ( a ) inh 86 3 ufp ?1 pulh pull h (index register high) from stack sp (sp + $0001); pull ( h ) inh 8a 3 ufp ?1 pulx pull x (index register low) from stack sp (sp + $0001); pull ( x ) inh 88 3 ufp ?1 rol opr8a rola rolx rol oprx8,x rol ,x rol oprx8,sp rotate left through carry dir inh inh ix1 ix sp1 39 49 59 69 79 9e 69 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 ror opr8a rora rorx ror oprx8 ,x ror ,x ror oprx8 ,sp rotate right through carry dir inh inh ix1 ix sp1 36 46 56 66 76 9e 66 dd ff ff 5 1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 11 table 7-2. instruction set summary (sheet 6 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c c b0 b7 b0 b7 c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 130 freescale semiconductor rsp reset stack pointer (low byte) spl $ff (high byte not affected) inh 9c 1 p ?1 rti return from interrupt sp (sp) + $0001; pull (ccr) sp (sp) + $0001; pull (a) sp (sp) + $0001; pull (x) sp (sp) + $0001; pull (pch) sp (sp) + $0001; pull (pcl) inh 80 9 uuuuufppp ? 11 ? ? ? ? ? rts return from subroutine sp sp + $0001; pull (pch) sp sp + $0001; pull (pcl) inh 81 5 ufppp ?1 sbc # opr8i sbc opr8a sbc opr16a sbc oprx16 ,x sbc oprx8,x sbc ,x sbc oprx16 ,sp sbc oprx8,sp subtract with carry a (a) ?(m) ?(c) imm dir ext ix2 ix1 ix sp2 sp1 a2 b2 c2 d2 e2 f2 9e d2 9e e2 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp ? 11 ? ? ? sec set carry bit (c 1) inh 99 1 p ?1 ? sei set interrupt mask bit (i 1) inh 9b 1 p ?1 1 sta opr8a sta opr16a sta oprx16,x sta oprx8 ,x sta ,x sta oprx16,sp sta oprx8,sp store accumulator in memory m (a) dir ext ix2 ix1 ix sp2 sp1 b7 c7 d7 e7 f7 9e d7 9e e7 dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 011 ? ? sthx opr8a sthx opr16a sthx oprx8,sp store h:x (index reg.) (m:m + $0001) (h:x) dir ext sp1 35 96 9e ff dd hh ll ff 4 5 5 wwpp pwwpp pwwpp 011 ? ? stop enable interrupts: stop processing refer to mcu documentation i bit 0; stop processing inh 8e 2 fp... ?1 0 stx opr8a stx opr16a stx oprx16,x stx oprx8,x stx ,x stx oprx16,sp stx oprx8,sp store x (low 8 bits of index register) in memory m (x) dir ext ix2 ix1 ix sp2 sp1 bf cf df ef ff 9e df 9e ef dd hh ll ee ff ff ee ff ff 3 4 4 3 2 5 4 wpp pwpp pwpp wpp wp ppwpp pwpp 011 ? ? table 7-2. instruction set summary (sheet 7 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 131 sub # opr8i sub opr8a sub opr16a sub oprx16 ,x sub oprx8,x sub ,x sub oprx16 ,sp sub oprx8,sp subtract a (a) ?(m) imm dir ext ix2 ix1 ix sp2 sp1 a0 b0 c0 d0 e0 f0 9e d0 9e e0 ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 11 swi software interrupt pc (pc) + $0001 push (pcl); sp (sp) ?$0001 push (pch); sp (sp) ?$0001 push (x); sp (sp) ?$0001 push (a); sp (sp) ?$0001 push (ccr); sp (sp) ?$0001 i 1; pch interrupt vector high byte pcl interrupt vector low byte inh 83 11 sssssvvfppp ?1 1 tap transfer accumulator to ccr ccr (a) inh 84 1 p 11 tax transfer accumulator to x (index register low) x (a) inh 97 1 p ?1 tpa transfer ccr to accumulator a (ccr) inh 85 1 p ?1 tst opr8a tsta tstx tst oprx8 ,x tst ,x tst oprx8,sp test for negative or zero (m) ?$00 (a) ?$00 (x) ?$00 (m) ?$00 (m) ?$00 (m) ?$00 dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e 6d dd ff ff 4 1 1 4 3 5 rfpp p p rfpp rfp prfpp 011 tsx transfer sp to index reg. h:x (sp) + $0001 inh 95 2 fp ?1 txa transfer x (index reg. low) to accumulator a (x) inh 9f 1 p ?1 table 7-2. instruction set summary (sheet 8 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 132 freescale semiconductor txs transfer index reg. to sp sp (h:x) ?$0001 inh 94 2 fp ?1 wait enable interrupts; wait for interrupt i bit 0; halt cpu inh 8f 2+ fp... ?1 0 source form: everything in the source forms columns, except expressions in italic characters , is literal information which must appear in the assembly source ?e exactly as shown. the initial 3- to 5-letter mnemonic and the characters (#, ( ) and +) are always a literal characters. n any label or expression that evaluates to a single integer in the range 0-7. opr8i any label or expression that evaluates to an 8-bit immediate value. opr16i any label or expression that evaluates to a 16-bit immediate value. opr8a any label or expression that evaluates to an 8-bit direct-page address ($00xx). opr16a any label or expression that evaluates to a 16-bit address. oprx8 any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing. oprx16 any label or expression that evaluates to a 16-bit value, used for indexed addressing. rel any label or expression that refers to an address that is within ?28 to +127 locations from the start of the next instruction. operation symbols: a accumulator ccr condition code register h index register high byte m memory location n any bit opr operand (one or two bytes) pc program counter pch program counter high byte pcl program counter low byte rel relative program counter offset byte sp stack pointer spl stack pointer low byte x index register low byte & logical and | logical or logical exclusive or ( ) contents of + add subtract, negation (twos complement) multiply divide # immediate value loaded with : concatenated with addressing modes: dir direct addressing mode ext extended addressing mode imm immediate addressing mode inh inherent addressing mode ix indexed, no offset addressing mode ix1 indexed, 8-bit offset addressing mode ix2 indexed, 16-bit offset addressing mode ix+ indexed, no offset, post increment addressing mode ix1+ indexed, 8-bit offset, post increment addressing mode rel relative addressing mode sp1 stack pointer, 8-bit offset addressing mode sp2 stack pointer 16-bit offset addressing mode cycle-by-cycle codes: f free cycle. this indicates a cycle where the cpu does not require use of the system buses. an f cycle is always one cycle of the system bus clock and is always a read cycle. p program fetch; read from next consecutive location in program memory r read 8-bit operand s push (write) one byte onto stack u pop (read) one byte from stack v read vector from $ffxx (high byte ?st) w write 8-bit operand ccr bits: v over?w bit h half-carry bit i interrupt mask n negative bit z zero bit c carry/borrow bit ccr effects: set or cleared not affected u unde?ed table 7-2. instruction set summary (sheet 9 of 9) source form operation address mode object code cycles cyc-by-cyc details affect on ccr v 1 1 h i n z c
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 133 table 7-3. opcode map (sheet 1 of 2) bit-manipulation branch read-modify-write control register/memory 00 5 brset0 3 dir 10 5 bset0 2 dir 20 3 bra 2 rel 30 5 neg 2 dir 40 1 nega 1 inh 50 1 negx 1 inh 60 5 neg 2 ix1 70 4 neg 1ix 80 9 rti 1 inh 90 3 bge 2 rel a0 2 sub 2 imm b0 3 sub 2 dir c0 4 sub 3 ext d0 4 sub 3 ix2 e0 3 sub 2ix1 f0 3 sub 1ix 01 5 brclr0 3 dir 11 5 bclr0 2 dir 21 3 brn 2 rel 31 5 cbeq 3 dir 41 4 cbeqa 3 imm 51 4 cbeqx 3imm 61 5 cbeq 3 ix1+ 71 5 cbeq 2 ix+ 81 6 rts 1 inh 91 3 blt 2 rel a1 2 cmp 2 imm b1 3 cmp 2 dir c1 4 cmp 3 ext d1 4 cmp 3 ix2 e1 3 cmp 2ix1 f1 3 cmp 1ix 02 5 brset1 3 dir 12 5 bset1 2 dir 22 3 bhi 2 rel 32 5 ldhx 3 ext 42 5 mul 1 inh 52 6 div 1 inh 62 1 nsa 1 inh 72 1 daa 1 inh 82 5+ bgnd 1 inh 92 3 bgt 2 rel a2 2 sbc 2 imm b2 3 sbc 2 dir c2 4 sbc 3 ext d2 4 sbc 3 ix2 e2 3 sbc 2ix1 f2 3 sbc 1ix 03 5 brclr1 3 dir 13 5 bclr1 2 dir 23 3 bls 2 rel 33 5 com 2 dir 43 1 coma 1 inh 53 1 comx 1 inh 63 5 com 2 ix1 73 4 com 1ix 83 11 swi 1 inh 93 3 ble 2 rel a3 2 cpx 2 imm b3 3 cpx 2 dir c3 4 cpx 3 ext d3 4 cpx 3 ix2 e3 3 cpx 2ix1 f3 3 cpx 1ix 04 5 brset2 3 dir 14 5 bset2 2 dir 24 3 bcc 2 rel 34 5 lsr 2 dir 44 1 lsra 1 inh 54 1 lsrx 1 inh 64 5 lsr 2 ix1 74 4 lsr 1ix 84 1 ta p 1 inh 94 2 txs 1 inh a4 2 and 2 imm b4 3 and 2 dir c4 4 and 3 ext d4 4 and 3 ix2 e4 3 and 2ix1 f4 3 and 1ix 05 5 brclr2 3 dir 15 5 bclr2 2 dir 25 3 bcs 2 rel 35 4 sthx 2 dir 45 3 ldhx 3 imm 55 4 ldhx 2 dir 65 3 cphx 3imm 75 5 cphx 2 dir 85 1 tpa 1 inh 95 2 tsx 1 inh a5 2 bit 2 imm b5 3 bit 2 dir c5 4 bit 3 ext d5 4 bit 3 ix2 e5 3 bit 2ix1 f5 3 bit 1ix 06 5 brset3 3 dir 16 5 bset3 2 dir 26 3 bne 2 rel 36 5 ror 2 dir 46 1 rora 1 inh 56 1 rorx 1 inh 66 5 ror 2 ix1 76 4 ror 1ix 86 3 pula 1 inh 96 5 sthx 3 ext a6 2 lda 2 imm b6 3 lda 2 dir c6 4 lda 3 ext d6 4 lda 3 ix2 e6 3 lda 2ix1 f6 3 lda 1ix 07 5 brclr3 3 dir 17 5 bclr3 2 dir 27 3 beq 2 rel 37 5 asr 2 dir 47 1 asra 1 inh 57 1 asrx 1 inh 67 5 asr 2 ix1 77 4 asr 1ix 87 2 psha 1 inh 97 1 ta x 1 inh a7 2 ais 2 imm b7 3 sta 2 dir c7 4 sta 3 ext d7 4 sta 3 ix2 e7 3 sta 2ix1 f7 2 sta 1ix 08 5 brset4 3 dir 18 5 bset4 2 dir 28 3 bhcc 2 rel 38 5 lsl 2 dir 48 1 lsla 1 inh 58 1 lslx 1 inh 68 5 lsl 2 ix1 78 4 lsl 1ix 88 3 pulx 1 inh 98 1 clc 1 inh a8 2 eor 2 imm b8 3 eor 2 dir c8 4 eor 3 ext d8 4 eor 3 ix2 e8 3 eor 2ix1 f8 3 eor 1ix 09 5 brclr4 3 dir 19 5 bclr4 2 dir 29 3 bhcs 2 rel 39 5 rol 2 dir 49 1 rola 1 inh 59 1 rolx 1 inh 69 5 rol 2 ix1 79 4 rol 1ix 89 2 pshx 1 inh 99 1 sec 1 inh a9 2 adc 2 imm b9 3 adc 2 dir c9 4 adc 3 ext d9 4 adc 3 ix2 e9 3 adc 2ix1 f9 3 adc 1ix 0a 5 brset5 3 dir 1a 5 bset5 2 dir 2a 3 bpl 2 rel 3a 5 dec 2 dir 4a 1 deca 1 inh 5a 1 decx 1 inh 6a 5 dec 2 ix1 7a 4 dec 1ix 8a 3 pulh 1 inh 9a 1 cli 1 inh aa 2 ora 2 imm ba 3 ora 2 dir ca 4 ora 3 ext da 4 ora 3 ix2 ea 3 ora 2ix1 fa 3 ora 1ix 0b 5 brclr5 3 dir 1b 5 bclr5 2 dir 2b 3 bmi 2 rel 3b 7 dbnz 3 dir 4b 4 dbnza 2 inh 5b 4 dbnzx 2 inh 6b 7 dbnz 3 ix1 7b 6 dbnz 2ix 8b 2 pshh 1 inh 9b 1 sei 1 inh ab 2 add 2 imm bb 3 add 2 dir cb 4 add 3 ext db 4 add 3 ix2 eb 3 add 2ix1 fb 3 add 1ix 0c 5 brset6 3 dir 1c 5 bset6 2 dir 2c 3 bmc 2 rel 3c 5 inc 2 dir 4c 1 inca 1 inh 5c 1 incx 1 inh 6c 5 inc 2 ix1 7c 4 inc 1ix 8c 1 clrh 1 inh 9c 1 rsp 1 inh bc 3 jmp 2 dir cc 4 jmp 3 ext dc 4 jmp 3 ix2 ec 3 jmp 2ix1 fc 3 jmp 1ix 0d 5 brclr6 3 dir 1d 5 bclr6 2 dir 2d 3 bms 2 rel 3d 4 tst 2 dir 4d 1 tsta 1 inh 5d 1 tstx 1 inh 6d 4 tst 2 ix1 7d 3 tst 1ix 9d 1 nop 1 inh ad 5 bsr 2 rel bd 5 jsr 2 dir cd 6 jsr 3 ext dd 6 jsr 3 ix2 ed 5 jsr 2ix1 fd 5 jsr 1ix 0e 5 brset7 3 dir 1e 5 bset7 2 dir 2e 3 bil 2 rel 3e 6 cphx 3 ext 4e 5 mov 3dd 5e 5 mov 2 dix+ 6e 4 mov 3imd 7e 5 mov 2 ix+d 8e 2+ stop 1 inh 9e page 2 ae 2 ldx 2 imm be 3 ldx 2 dir ce 4 ldx 3 ext de 4 ldx 3 ix2 ee 3 ldx 2ix1 fe 3 ldx 1ix 0f 5 brclr7 3 dir 1f 5 bclr7 2 dir 2f 3 bih 2 rel 3f 5 clr 2 dir 4f 1 clra 1 inh 5f 1 clrx 1 inh 6f 5 clr 2 ix1 7f 4 clr 1ix 8f 2+ wait 1 inh 9f 1 txa 1 inh af 2 aix 2 imm bf 3 stx 2 dir cf 4 stx 3 ext df 4 stx 3 ix2 ef 3 stx 2ix1 ff 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment opcode in hexadecimal number of bytes f0 3 sub 1ix hcs08 cycles instruction mnemonic addressing mode
chapter 7 central processor unit (s08cpuv3) mc9s08de60 series data sheet, rev. 3 134 freescale semiconductor bit-manipulation branch read-modify-write control register/memory 9e60 6 neg 3 sp1 9ed0 5 sub 4 sp2 9ee0 4 sub 3sp1 9e61 6 cbeq 4 sp1 9ed1 5 cmp 4 sp2 9ee1 4 cmp 3sp1 9ed2 5 sbc 4 sp2 9ee2 4 sbc 3sp1 9e63 6 com 3 sp1 9ed3 5 cpx 4 sp2 9ee3 4 cpx 3sp1 9ef3 6 cphx 3 sp1 9e64 6 lsr 3 sp1 9ed4 5 and 4 sp2 9ee4 4 and 3sp1 9ed5 5 bit 4 sp2 9ee5 4 bit 3sp1 9e66 6 ror 3 sp1 9ed6 5 lda 4 sp2 9ee6 4 lda 3sp1 9e67 6 asr 3 sp1 9ed7 5 sta 4 sp2 9ee7 4 sta 3sp1 9e68 6 lsl 3 sp1 9ed8 5 eor 4 sp2 9ee8 4 eor 3sp1 9e69 6 rol 3 sp1 9ed9 5 adc 4 sp2 9ee9 4 adc 3sp1 9e6a 6 dec 3 sp1 9eda 5 ora 4 sp2 9eea 4 ora 3sp1 9e6b 8 dbnz 4 sp1 9edb 5 add 4 sp2 9eeb 4 add 3sp1 9e6c 6 inc 3 sp1 9e6d 5 tst 3 sp1 9eae 5 ldhx 2ix 9ebe 6 ldhx 4 ix2 9ece 5 ldhx 3 ix1 9ede 5 ldx 4 sp2 9eee 4 ldx 3sp1 9efe 5 ldhx 3 sp1 9e6f 6 clr 3 sp1 9edf 5 stx 4 sp2 9eef 4 stx 3sp1 9eff 5 sthx 3 sp1 inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd dir to dir imd imm to dir ix1+ indexed, 1-byte offset with ix+d ix+ to dir dix+ dir to ix+ post increment note: all sheet 2 opcodes are preceded by the page 2 prebyte (9e) prebyte (9e) and opcode in hexadecimal number of bytes 9e60 6 neg 3 sp1 hcs08 cycles instruction mnemonic addressing mode table 7-3. opcode map (sheet 2 of 2)
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 135 chapter 8 multi-purpose clock generator (s08mcgv1) 8.1 introduction the multi-purpose clock generator (mcg) module provides several clock source choices for the mcu. the module contains a frequency-locked loop (fll) and a phase-locked loop (pll) that are controllable by either an internal or an external reference clock. the module can select either of the fll or pll clocks, or either of the internal or external reference clocks as a source for the mcu system clock. whichever clock source is chosen, it is passed through a reduced bus divider which allows a lower output clock frequency to be derived. the mcg also controls an external oscillator (xosc) for the use of a crystal or resonator as the external reference clock. all devices in the mc9s08de60 series feature the mcg module. note refer to section 1.3, ?ystem clock distribution , for detailed view of the distribution clock sources throughout the chip.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 136 freescale semiconductor figure 8-1. mc9s08de60/32 block diagram emphasizing the mcg block and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 137 8.1.1 features key features of the mcg module are: frequency-locked loop (fll) 0.2% resolution using internal 32-khz reference 2% deviation over voltage and temperature using internal 32-khz reference internal or external reference can be used to control the fll phase-locked loop (pll) voltage-controlled oscillator (vco) modulo vco frequency divider phase/frequency detector integrated loop ?ter lock detector with interrupt capability internal reference clock nine trim bits for accuracy can be selected as the clock source for the mcu external reference clock control for external oscillator clock monitor with reset capability can be selected as the clock source for the mcu reference divider is provided clock source selected can be divided down by 1, 2, 4, or 8 bdc clock (mcglclk) is provided as a constant divide by 2 of the dco output whether in an fll or pll mode.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 138 freescale semiconductor figure 8-2. multi-purpose clock generator (mcg) block diagram dco filter rdiv trim external oscillator irefs (xosc) clks n=0-7 / 2 n n=0-3 / 2 n internal reference clock bdiv 9 mcglclk mcgout mcgirclk erefs range erefsten hgo irefsten mcgerclk lp mcgffclk dcoout fll rdiv_clk pll vdiv /(4,8,12,...,40) vco phase detector charge pump internal filter lock detector lock clock monitor oscinit vcoout multi-purpose clock generator (mcg) lp erclken irclken cme loc / 2 plls lols mcgffclkvalid
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 139 8.1.2 modes of operation there are nine modes of operation for the mcg: fll engaged internal (fei) fll engaged external (fee) fll bypassed internal (fbi) fll bypassed external (fbe) pll engaged external (pee) pll bypassed external (pbe) bypassed low power internal (blpi) bypassed low power external (blpe) stop for details see section 8.4.1, ?perational modes . 8.2 external signal description there are no mcg signals that connect off chip.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 140 freescale semiconductor 8.3 register de?ition 8.3.1 mcg control register 1 (mcgc1) 7 654 3 210 r clks rdiv irefs irclken irefsten w reset: 0 0 0 0 0 1 0 0 figure 8-3. mcg control register 1 (mcgc1) table 8-1. mcg control register 1 field descriptions field description 7:6 clks clock source select ?selects the system clock source. 00 encoding 0 ?output of fll or pll is selected. 01 encoding 1 ?internal reference clock is selected. 10 encoding 2 ?external reference clock is selected. 11 encoding 3 ?reserved, defaults to 00. 5:3 rdiv reference divider ?selects the amount to divide down the reference clock selected by the irefs bit. if the fll is selected, the resulting frequency must be in the range 31.25 khz to 39.0625 khz. if the pll is selected, the resulting frequency must be in the range 1 mhz to 2 mhz. 000 encoding 0 ?divides reference clock by 1 (reset default) 001 encoding 1 ?divides reference clock by 2 010 encoding 2 ?divides reference clock by 4 011 encoding 3 ?divides reference clock by 8 100 encoding 4 ?divides reference clock by 16 101 encoding 5 ?divides reference clock by 32 110 encoding 6 ?divides reference clock by 64 111 encoding 7 ?divides reference clock by 128 2 irefs internal reference select ?selects the reference clock source. 1 internal reference clock selected 0 external reference clock selected 1 irclken internal reference clock enable ?enables the internal reference clock for use as mcgirclk. 1 mcgirclk active 0 mcgirclk inactive 0 irefsten internal reference stop enable controls whether or not the internal reference clock remains enabled when the mcg enters stop mode. 1 internal reference clock stays enabled in stop if irclken is set or if mcg is in fei, fbi, or blpi mode before entering stop 0 internal reference clock is disabled in stop
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 141 8.3.2 mcg control register 2 (mcgc2) 76543210 r bdiv range hgo lp erefs erclken erefsten w reset: 0 1 0 0 0 0 0 0 figure 8-4. mcg control register 2 (mcgc2) table 8-2. mcg control register 2 field descriptions field description 7:6 bdiv bus frequency divider selects the amount to divide down the clock source selected by the clks bits in the mcgc1 register. this controls the bus frequency. 00 encoding 0 ?divides selected clock by 1 01 encoding 1 ?divides selected clock by 2 (reset default) 10 encoding 2 ?divides selected clock by 4 11 encoding 3 ?divides selected clock by 8 5 range frequency range select ?selects the frequency range for the external oscillator or external clock source. 1 high frequency range selected for the external oscillator of 1 mhz to 16 mhz (1 mhz to 40 mhz for external clock source) 0 low frequency range selected for the external oscillator of 32 khz to 100 khz (32 khz to 1 mhz for external clock source) 4 hgo high gain oscillator select ?controls the external oscillator mode of operation. 1 con?ure external oscillator for high gain operation 0 con?ure external oscillator for low power operation 3 lp low power select ?controls whether the fll (or pll) is disabled in bypassed modes. 1 fll (or pll) is disabled in bypass modes (lower power) . 0 fll (or pll) is not disabled in bypass modes. 2 erefs external reference select ?selects the source for the external reference clock. 1 oscillator requested 0 external clock source requested 1 erclken external reference enable ?enables the external reference clock for use as mcgerclk. 1 mcgerclk active 0 mcgerclk inactive 0 erefsten external reference stop enable controls whether or not the external reference clock remains enabled when the mcg enters stop mode. 1 external reference clock stays enabled in stop if erclken is set or if mcg is in fee, fbe, pee, pbe, or blpe mode before entering stop 0 external reference clock is disabled in stop
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 142 freescale semiconductor 8.3.3 mcg trim register (mcgtrm) 7 654 3 210 r trim w por: 1 0 0 0 0 0 0 0 reset: u u u u u u u u figure 8-5. mcg trim register (mcgtrm) table 8-3. mcg trim register field descriptions field description 7:0 trim mcg trim setting controls the internal reference clock frequency by controlling the internal reference clock period. the trim bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). increasing the binary value in trim will increase the period, and decreasing the value will decrease the period. an additional ?e trim bit is available in mcgsc as the ftrim bit. if a trim[7:0] value stored in nonvolatile memory is to be used, its the users responsibility to copy that value from the nonvolatile memory location to this register.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 143 8.3.4 mcg status and control register (mcgsc) 7 654 3 210 r lols lock pllst irefst clkst oscinit ftrim w por: reset: 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 u figure 8-6. mcg status and control register (mcgsc) table 8-4. mcg status and control register field descriptions field description 7 lols loss of lock status ?this bit is a sticky indication of lock status for the fll or pll. lols is set when lock detection is enabled and after acquiring lock, the fll or pll output frequency has fallen outside the lock exit frequency tolerance, d unl . lolie determines whether an interrupt request is made when set. lols is cleared by reset or by writing a logic 1 to lols when lols is set. writing a logic 0 to lols has no effect. 0 fll or pll has not lost lock since lols was last cleared. 1 fll or pll has lost lock since lols was last cleared. 6 lock lock status ?indicates whether the fll or pll has acquired lock. lock detection is disabled when both the fll and pll are disabled. if the lock status bit is set then changing the value of any of the following bits irefs, plls, rdiv[2:0], trim[7:0] (if in fei or fbi modes), or vdiv[3:0] (if in pbe or pee modes), will cause the lock status bit to clear and stay cleared until the fll or pll has reacquired lock. stop mode entry will also cause the lock status bit to clear and stay cleared until the fll or pll has reacquired lock. entry into blpi or blpe mode will also cause the lock status bit to clear and stay cleared until the mcg has exited these modes and the fll or pll has reacquired lock. 0 fll or pll is currently unlocked. 1 fll or pll is currently locked. 5 pllst pll select status ?the pllst bit indicates the current source for the plls clock. the pllst bit does not update immediately after a write to the plls bit due to internal synchronization between clock domains. 0 source of plls clock is fll clock. 1 source of plls clock is pll clock. 4 irefst internal reference status the irefst bit indicates the current source for the reference clock. the irefst bit does not update immediately after a write to the irefs bit due to internal synchronization between clock domains. 0 source of reference clock is external reference clock (oscillator or external clock source as determined by the erefs bit in the mcgc2 register). 1 source of reference clock is internal reference clock. 3:2 clkst clock mode status ?the clkst bits indicate the current clock mode. the clkst bits do not update immediately after a write to the clks bits due to internal synchronization between clock domains. 00 encoding 0 ?output of fll is selected. 01 encoding 1 ?internal reference clock is selected. 10 encoding 2 ?external reference clock is selected. 11 encoding 3 ?output of pll is selected.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 144 freescale semiconductor 8.3.5 mcg control register 3 (mcgc3) 1 oscinit osc initialization if the external reference clock is selected by erclken or by the mcg being in fee, fbe, pee, pbe, or blpe mode, and if erefs is set, then this bit is set after the initialization cycles of the external oscillator clock have completed. this bit is only cleared when either erefs is cleared or when the mcg is in either fei, fbi, or blpi mode and erclken is cleared. 0 ftrim mcg fine trim ?controls the smallest adjustment of the internal reference clock frequency. setting ftrim will increase the period and clearing ftrim will decrease the period by the smallest amount possible. if an ftrim value stored in nonvolatile memory is to be used, its the users responsibility to copy that value from the nonvolatile memory location to this registers ftrim bit. 7 654 3 210 r lolie plls cme 0 vdiv w reset: 0 0 0 0 0 0 0 1 figure 8-7. mcg pll register (mcgpll) table 8-5. mcg pll register field descriptions field description 7 lolie loss of lock interrupt enable determines if an interrupt request is made following a loss of lock indication. the lolie bit only has an effect when lols is set. 0 no request on loss of lock. 1 generate an interrupt request on loss of lock. 6 plls pll select ?controls whether the pll or fll is selected. if the plls bit is clear, the pll is disabled in all modes. if the plls is set, the fll is disabled in all modes. 1 pll is selected 0 fll is selected table 8-4. mcg status and control register field descriptions (continued) field description
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 145 5 cme clock monitor enable determines if a reset request is made following a loss of external clock indication. the cme bit should only be set to a logic 1 when either the mcg is in an operational mode that uses the external clock (fee, fbe, pee, pbe, or blpe) or the external reference is enabled (erclken=1 in the mcgc2 register). whenever the cme bit is set to a logic 1, the value of the range bit in the mcgc2 register should not be changed. 0 clock monitor is disabled. 1 generate a reset request on loss of external clock. 3:0 vdiv vco divider ?selects the amount to divide down the vco output of pll. the vdiv bits establish the multiplication factor (m) applied to the reference clock frequency. 0000 encoding 0 ?reserved. 0001 encoding 1 ?multiply by 4. 0010 encoding 2 ?multiply by 8. 0011 encoding 3 ?multiply by 12. 0100 encoding 4 ?multiply by 16. 0101 encoding 5 ?multiply by 20. 0110 encoding 6 ?multiply by 24. 0111 encoding 7 ?multiply by 28. 1000 encoding 8 ?multiply by 32. 1001 encoding 9 ?multiply by 36. 1010 encoding 10 ?multiply by 40. 1011 encoding 11 ?reserved (default to m=40). 11xx encoding 12-15 ?reserved (default to m=40). table 8-5. mcg pll register field descriptions (continued) field description
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 146 freescale semiconductor 8.4 functional description 8.4.1 operational modes figure 8-8. clock switching modes entered from any state when mcu enters stop returns to state that was active before mcu entered stop, unless reset occurs while in stop. stop pll bypassed external (pbe) pll engaged external (pee) fll engaged external (fee) fll engaged internal (fei) fll bypassed external (fbe) fll bypassed internal (fbi) irefs=1 clks=00 plls=0 irefs=0 clks=00 plls=0 irefs=1 clks=01 plls=0 irefs=0 clks=10 plls=0 irefs=0 clks=00 plls=1 irefs=0 clks=10 plls=1 irefs=0 clks=10 bdm disabled and lp=1 irefs=1 clks=01 plls=0 bdm disabled and lp=1 bypassed low power internal (blpi) bypassed low power external (blpe) bdm enabled or lp=0 bdm enabled or lp=0 bdm enabled or lp=0
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 147 the nine states of the mcg are shown as a state diagram and are described below. the arrows indicate the allowed movements between the states. 8.4.1.1 fll engaged internal (fei) fll engaged internal (fei) is the default mode of operation and is entered when all the following conditions occur: clks bits are written to 00 irefs bit is written to 1 plls bit is written to 0 rdiv bits are written to 000. since the internal reference clock frequency should already be in the range of 31.25 khz to 39.0625 khz after it is trimmed, no further frequency divide is necessary. in fll engaged internal mode, the mcgout clock is derived from the fll clock, which is controlled by the internal reference clock. the fll clock frequency locks to 1024 times the reference frequency, as selected by the rdiv bits. the mcglclk is derived from the fll and the pll is disabled in a low power state. 8.4.1.2 fll engaged external (fee) the fll engaged external (fee) mode is entered when all the following conditions occur: clks bits are written to 00 irefs bit is written to 0 plls bit is written to 0 rdiv bits are written to divide reference clock to be within the range of 31.25 khz to 39.0625 khz in fll engaged external mode, the mcgout clock is derived from the fll clock which is controlled by the external reference clock. the external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source.the fll clock frequency locks to 1024 times the reference frequency, as selected by the rdiv bits. the mcglclk is derived from the fll and the pll is disabled in a low power state. 8.4.1.3 fll bypassed internal (fbi) in fll bypassed internal (fbi) mode, the mcgout clock is derived from the internal reference clock and the fll is operational but its output clock is not used. this mode is useful to allow the fll to acquire its target frequency while the mcgout clock is driven from the internal reference clock. the fll bypassed internal mode is entered when all the following conditions occur: clks bits are written to 01 irefs bit is written to 1 plls bit is written to 0 rdiv bits are written to 000. since the internal reference clock frequency should already be in the range of 31.25 khz to 39.0625 khz after it is trimmed, no further frequency divide is necessary.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 148 freescale semiconductor lp bit is written to 0 in fll bypassed internal mode, the mcgout clock is derived from the internal reference clock. the fll clock is controlled by the internal reference clock, and the fll clock frequency locks to 1024 times the reference frequency, as selected by the rdiv bits. the mcglclk is derived from the fll and the pll is disabled in a low power state. 8.4.1.4 fll bypassed external (fbe) in fll bypassed external (fbe) mode, the mcgout clock is derived from the external reference clock and the fll is operational but its output clock is not used. this mode is useful to allow the fll to acquire its target frequency while the mcgout clock is driven from the external reference clock. the fll bypassed external mode is entered when all the following conditions occur: clks bits are written to 10 irefs bit is written to 0 plls bit is written to 0 rdiv bits are written to divide reference clock to be within the range of 31.25 khz to 39.0625 khz lp bit is written to 0 in fll bypassed external mode, the mcgout clock is derived from the external reference clock. the external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source.the fll clock is controlled by the external reference clock, and the fll clock frequency locks to 1024 times the reference frequency, as selected by the rdiv bits. the mcglclk is derived from the fll and the pll is disabled in a low power state. note it is possible to brie? operate in fbe mode with an fll reference clock frequency that is greater than the speci?d maximum frequency. this can be necessary in applications that operate in pee mode using an external crystal with a frequency above 5 mhz. please see 8.5.2.4, ?xample # 4: moving from fei to pee mode: external crystal = 8 mhz, bus frequency = 8 mhz for a detailed example. 8.4.1.5 pll engaged external (pee) the pll engaged external (pee) mode is entered when all the following conditions occur: clks bits are written to 00 irefs bit is written to 0 plls bit is written to 1 rdiv bits are written to divide reference clock to be within the range of 1 mhz to 2 mhz in pll engaged external mode, the mcgout clock is derived from the pll clock which is controlled by the external reference clock. the external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source the pll clock frequency locks to a
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 149 multiplication factor, as selected by the vdiv bits, times the reference frequency, as selected by the rdiv bits. if bdm is enabled then the mcglclk is derived from the dco (open-loop mode) divided by two. if bdm is not enabled then the fll is disabled in a low power state. 8.4.1.6 pll bypassed external (pbe) in pll bypassed external (pbe) mode, the mcgout clock is derived from the external reference clock and the pll is operational but its output clock is not used. this mode is useful to allow the pll to acquire its target frequency while the mcgout clock is driven from the external reference clock. the pll bypassed external mode is entered when all the following conditions occur: clks bits are written to 10 irefs bit is written to 0 plls bit is written to 1 rdiv bits are written to divide reference clock to be within the range of 1 mhz to 2 mhz lp bit is written to 0 in pll bypassed external mode, the mcgout clock is derived from the external reference clock. the external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. the pll clock frequency locks to a multiplication factor, as selected by the vdiv bits, times the reference frequency, as selected by the rdiv bits. if bdm is enabled then the mcglclk is derived from the dco (open-loop mode) divided by two. if bdm is not enabled then the fll is disabled in a low power state. 8.4.1.7 bypassed low power internal (blpi) the bypassed low power internal (blpi) mode is entered when all the following conditions occur: clks bits are written to 01 irefs bit is written to 1 plls bit is written to 0 lp bit is written to 1 bdm mode is not active in bypassed low power internal mode, the mcgout clock is derived from the internal reference clock. the pll and the fll are disabled at all times in blpi mode and the mcglclk will not be available for bdc communications if the bdm becomes active the mode will switch to fll bypassed internal (fbi) mode. 8.4.1.8 bypassed low power external (blpe) the bypassed low power external (blpe) mode is entered when all the following conditions occur: clks bits are written to 10 irefs bit is written to 0 plls bit is written to 0 or 1
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 150 freescale semiconductor lp bit is written to 1 bdm mode is not active in bypassed low power external mode, the mcgout clock is derived from the external reference clock. the external reference clock which is enabled can be an external crystal/resonator or it can be another external clock source. the pll and the fll are disabled at all times in blpe mode and the mcglclk will not be available for bdc communications. if the bdm becomes active the mode will switch to one of the bypassed external modes as determined by the state of the plls bit. 8.4.1.9 stop stop mode is entered whenever the mcu enters a stop state. in this mode, the fll and pll are disabled and all mcg clock signals are static except in the following cases: mcgirclk will be active in stop mode when all the following conditions occur: irclken = 1 irefsten = 1 mcgerclk will be active in stop mode when all the following conditions occur: erclken = 1 erefsten = 1 8.4.2 mode switching when switching between engaged internal and engaged external modes the irefs bit can be changed at anytime, but the rdiv bits must be changed simultaneously so that the reference frequency stays in the range required by the state of the plls bit (31.25 khz to 39.0625 khz if the fll is selected, or 1 mhz to 2 mhz if the pll is selected). after a change in the irefs value the fll or pll will begin locking again after the switch is completed. the completion of the switch is shown by the irefst bit . for the special case of entering stop mode immediately after switching to fbe mode, if the external clock and the internal clock are disabled in stop mode, (erefsten = 0 and irefsten = 0), it is necessary to allow 100us after the irefst bit is cleared to allow the internal reference to shutdown. for most cases the delay due to instruction execution times will be suf?ient. the clks bits can also be changed at anytime, but in order for the mcglclk to be con?ured correctly the rdiv bits must be changed simultaneously so that the reference frequency stays in the range required by the state of the plls bit (31.25 khz to 39.0625 khz if the fll is selected, or 1 mhz to 2mhz if the pll is selected). the actual switch to the newly selected clock will be shown by the clkst bits. if the newly selected clock is not available, the previous clock will remain selected. for details see figure 8-8 .
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 151 8.4.3 bus frequency divider the bdiv bits can be changed at anytime and the actual switch to the new frequency will occur immediately. 8.4.4 low power bit usage the low power bit (lp) is provided to allow the fll or pll to be disabled and thus conserve power when these systems are not being used. however, in some applications it may be desirable to enable the fll or pll and allow it to lock for maximum accuracy before switching to an engaged mode. do this by writing the lp bit to 0. 8.4.5 internal reference clock when irclken is set the internal reference clock signal will be presented as mcgirclk, which can be used as an additional clock source. the mcgirclk frequency can be re-targeted by trimming the period of the internal reference clock. this can be done by writing a new value to the trim bits in the mcgtrm register. writing a larger value will decrease the mcgirclk frequency, and writing a smaller value to the mcgtrm register will increase the mcgirclk frequency. the trim bits will effect the mcgout frequency if the mcg is in fll engaged internal (fei), fll bypassed internal (fbi), or bypassed low power internal (blpi) mode. the trim and ftrim value is initialized by por but is not affected by other resets. until mcgirclk is trimmed, programming low reference divider (rdiv) factors may result in mcgout frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing speci?ations (see the device overview chapter). if irefsten and irclken bits are both set, the internal reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. 8.4.6 external reference clock the mcg module can support an external reference clock with frequencies between 31.25 khz to 5 mhz in fee and fbe modes, 1 mhz to 16 mhz in pee and pbe modes, and 0 to 40 mhz in blpe mode. when erclken is set, the external reference clock signal will be presented as mcgerclk, which can be used as an additional clock source. when irefs = 1, the external reference clock will not be used by the fll or pll and will only be used as mcgerclk. in these modes, the frequency can be equal to the maximum frequency the chip-level timing speci?ations will support (see the device overview chapter). if erefsten and erclken bits are both set or the mcg is in fee, fbe, pee, pbe or blpe mode, the external reference clock will keep running during stop mode in order to provide a fast recovery upon exiting stop. if cme bit is written to 1, the clock monitor is enabled. if the external reference falls below a certain frequency (f loc_high or f loc_low depending on the range bit in the mcgc2), the mcu will reset. the loc bit in the system reset status (srs) register will be set to indicate the error.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 152 freescale semiconductor 8.4.7 fixed frequency clock the mcg presents the divided reference clock as mcgffclk for use as an additional clock source. the mcgffclk frequency must be no more than 1/4 of the mcgout frequency to be valid. because of this requirement, the mcgffclk is not valid in bypass modes for the following combinations of bdiv and rdiv values: bdiv=00 (divide by 1), rdiv < 010 bdiv=01 (divide by 2), rdiv < 011 when mcgffclk is valid then mcgffclkvalid is set to 1. when mcgffclk is not valid then mcgffclkvalid is set to 0. 8.5 initialization / application information this section describes how to initialize and con?ure the mcg module in application. the following sections include examples on how to initialize the mcg and properly switch between the various available modes. 8.5.1 mcg module initialization sequence the mcg comes out of reset con?ured for fei mode with the bdiv set for divide-by-2. the internal reference will stabilize in t irefst microseconds before the fll can acquire lock. as soon as the internal reference is stable, the fll will acquire lock in t ?_lock milliseconds. upon por, the internal reference will require trimming to guarantee an accurate clock. freescale recommends using flash location 0xffae for storing the ?e trim bit, ftrim in the mcgsc register, and 0xffaf for storing the 8-bit trim value in the mcgtrm register. the mcu will not automatically copy the values in these flash locations to the respective registers. therefore, user code must copy these values from flash to the registers. note the bdiv value should not be changed to divide-by-1 without ?st trimming the internal reference. failure to do so could result in the mcu running out of speci?ation. 8.5.1.1 initializing the mcg because the mcg comes out of reset in fei mode, the only mcg modes which can be directly switched to upon reset are fee, fbe, and fbi modes (see figure 8-8 ). reaching any of the other modes requires ?st con?uring the mcg for one of these three initial modes. care must be taken to check relevant status bits in the mcgsc register re?cting all con?uration changes within each mode. to change from fei mode to fee or fbe modes, follow this procedure: 1. enable the external clock source by setting the appropriate bits in mcgc2. 2. write to mcgc1 to select the clock mode.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 153 if entering fee, set rdiv appropriately, clear the irefs bit to switch to the external reference, and leave the clks bits at %00 so that the output of the fll is selected as the system clock source. if entering fbe, clear the irefs bit to switch to the external reference and change the clks bits to %10 so that the external reference clock is selected as the system clock source. the rdiv bits should also be set appropriately here according to the external reference frequency because although the fll is bypassed, it is still on in fbe mode. the internal reference can optionally be kept running by setting the irclken bit. this is useful if the application will switch back and forth between internal and external modes. for minimum power consumption, leave the internal reference disabled while in an external clock mode. 3. after the proper con?uration bits have been set, wait for the affected bits in the mcgsc register to be changed appropriately, re?cting that the mcg has moved into the proper mode. if erclken was set in step 1 or the mcg is in fee, fbe, pee, pbe, or blpe mode, and erefs was also set in step 1, wait here for the oscinit bit to become set indicating that the external clock source has ?ished its initialization cycles and stabilized. typical crystal startup times are given in appendix a, ?lectrical characteristics? if in fee mode, check to make sure the irefst bit is cleared and the lock bit is set before moving on. if in fbe mode, check to make sure the irefst bit is cleared, the lock bit is set, and the clkst bits have changed to %10 indicating the external reference clock has been appropriately selected. although the fll is bypassed in fbe mode, it is still on and will lock in fbe mode. to change from fei clock mode to fbi clock mode, follow this procedure: 1. change the clks bits to %01 so that the internal reference clock is selected as the system clock source. 2. wait for the clkst bits in the mcgsc register to change to %01, indicating that the internal reference clock has been appropriately selected. 8.5.2 mcg mode switching when switching between operational modes of the mcg, certain con?uration bits must be changed in order to properly move from one mode to another. each time any of these bits are changed (plls, irefs, clks, or erefs), the corresponding bits in the mcgsc register (pllst, irefst, clkst, or oscinit) must be checked before moving on in the application software. additionally, care must be taken to ensure that the reference clock divider (rdiv) is set properly for the mode being switched to. for instance, in pee mode, if using a 4 mhz crystal, rdiv must be set to %001 (divide-by-2) or %010 (divide -by-4) in order to divide the external reference down to the required frequency between 1 and 2 mhz. the rdiv and irefs bits should always be set properly before changing the plls bit so that the fll or pll clock has an appropriate reference clock frequency to switch to.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 154 freescale semiconductor the table below shows mcgout frequency calculations using rdiv, bdiv, and vdiv settings for each clock mode. the bus frequency is equal to mcgout divided by 2. 1 r is the reference divider selected by the rdiv bits, b is the bus frequency divider selected by the bdiv bits, and m is the multiplier selected by the vdiv bits. this section will include 3 mode switching examples using a 4 mhz external crystal. if using an external clock source less than 1 mhz, the mcg should not be con?ured for any of the pll modes (pee and pbe). 8.5.2.1 example # 1: moving from fei to pee mode: external crystal = 4 mhz, bus frequency = 8 mhz in this example, the mcg will move through the proper operational modes from fei to pee mode until the 4 mhz crystal reference frequency is set to achieve a bus frequency of 8 mhz. because the mcg is in fei mode out of reset, this example also shows how to initialize the mcg for pee mode out of reset. first, the code sequence will be described. then a ?wchart will be included which illustrates the sequence. 1. first, fei must transition to fbe mode: a) mcgc2 = 0x36 (%00110110) bdiv (bits 7 and 6) set to %00, or divide-by-1 range (bit 5) set to 1 because the frequency of 4 mhz is within the high frequency range hgo (bit 4) set to 1 to con?ure external oscillator for high gain operation erefs (bit 2) set to 1, because a crystal is being used erclken (bit 1) set to 1 to ensure the external reference clock is active b) loop until oscinit (bit 1) in mcgsc is 1, indicating the crystal selected by the erefs bit has been initialized. table 8-6. mcgout frequency calculation options clock mode f mcgout 1 note fei (fll engaged internal) (f int * 1024) / b typical f mcgout = 16 mhz immediately after reset. rdiv bits set to %000. fee (fll engaged external) (f ext / r *1024) / b f ext / r must be in the range of 31.25 khz to 39.0625 khz fbe (fll bypassed external) f ext / b f ext / r must be in the range of 31.25 khz to 39.0625 khz fbi (fll bypassed internal) f int / b typical f int = 32 khz pee (pll engaged external) [(f ext / r) * m] / b f ext / r must be in the range of 1 mhz to 2 mhz pbe (pll bypassed external) f ext / b f ext / r must be in the range of 1 mhz to 2 mhz blpi (bypassed low power internal) f int / b blpe (bypassed low power external) f ext / b
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 155 c) mcgc1 = 0xb8 (%10111000) clks (bits 7 and 6) set to %10 in order to select external reference clock as system clock source rdiv (bits 5-3) set to %111, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll irefs (bit 2) cleared to 0, selecting the external reference clock d) loop until irefst (bit 4) in mcgsc is 0, indicating the external reference is the current source for the reference clock e) loop until clkst (bits 3 and 2) in mcgsc are %10, indicating that the external reference clock is selected to feed mcgout 2. then, fbe must transition either directly to pbe mode or ?st through blpe mode and then to pbe mode: a) blpe: if a transition through blpe mode is desired, ?st set lp (bit 3) in mcgc2 to 1. b) blpe/pbe: mcgc1 = 0x90 (%10010000) rdiv (bits 5-3) set to %010, or divide-by-4 because 4 mhz / 4 = 1 mhz which is in the 1 mhz to 2 mhz range required by the pll. in blpe mode, the con?uration of the rdiv does not matter because both the fll and pll are disabled. changing them only sets up the the dividers for pll usage in pbe mode c) blpe/pbe: mcgc3 = 0x44 (%01000100) plls (bit 6) set to 1, selects the pll. in blpe mode, changing this bit only prepares the mcg for pll usage in pbe mode vdiv (bits 3-0) set to %0100, or multiply-by-16 because 1 mhz reference * 16 = 16 mhz. in blpe mode, the con?uration of the vdiv bits does not matter because the pll is disabled. changing them only sets up the multiply value for pll usage in pbe mode d) blpe: if transitioning through blpe mode, clear lp (bit 3) in mcgc2 to 0 here to switch to pbe mode e) pbe: loop until pllst (bit 5) in mcgsc is set, indicating that the current source for the plls clock is the pll f) pbe: then loop until lock (bit 6) in mcgsc is set, indicating that the pll has acquired lock 3. last, pbe mode transitions into pee mode: a) mcgc1 = 0x10 (%00010000) clks (bits7 and 6) in mcgsc1 set to %00 in order to select the output of the pll as the system clock source b) loop until clkst (bits 3 and 2) in mcgsc are %11, indicating that the pll output is selected to feed mcgout in the current clock mode now, with an rdiv of divide-by-4, a bdiv of divide-by-1, and a vdiv of multiply-by-16, mcgout = [(4 mhz / 4) * 16] / 1 = 16 mhz, and the bus frequency is mcgout / 2, or 8 mhz
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 156 freescale semiconductor figure 8-9. flowchart of fei to pee mode transition using a 4 mhz crystal mcgc2 = $36 check oscinit = 1 ? mcgc1 = $b8 check irefst = 0? check clkst = %10? enter blpe mode ? mcgc2 = $3e (lp = 1) mcgc1 = $90 mcgc3 = $44 in blpe mode ? (lp=1) mcgc2 = $36 (lp = 0) check pllst = 1? mcgc1 = $10 check lock = 1? check clkst = %11? continue in pee mode start i n fei mode yes yes yes yes yes yes yes yes no no no no no no no no
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 157 8.5.2.2 example # 2: moving from pee to blpi mode: external crystal = 4 mhz, bus frequency =16 khz in this example, the mcg will move through the proper operational modes from pee mode with a 4 mhz crystal con?ured for an 8 mhz bus frequency (see previous example) to blpi mode with a 16 khz bus frequency.first, the code sequence will be described. then a ?wchart will be included which illustrates the sequence. 1. first, pee must transition to pbe mode: a) mcgc1 = 0x90 (%10010000) clks (bits 7 and 6) set to %10 in order to switch the system clock source to the external reference clock b) loop until clkst (bits 3 and 2) in mcgsc are %10, indicating that the external reference clock is selected to feed mcgout 2. then, pbe must transition either directly to fbe mode or ?st through blpe mode and then to fbe mode: a) blpe: if a transition through blpe mode is desired, ?st set lp (bit 3) in mcgc2 to 1 b) blpe/fbe: mcgc1 = 0xb8 (%10111000) rdiv (bits 5-3) set to %111, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll. in blpe mode, the con?uration of the rdiv does not matter because both the fll and pll are disabled. changing them only sets up the dividers for fll usage in fbe mode c) blpe/fbe: mcgc3 = 0x04 (%00000100) plls (bit 6) clear to 0 to select the fll. in blpe mode, changing this bit only prepares the mcg for fll usage in fbe mode. with plls = 0, the vdiv value does not matter. d) blpe: if transitioning through blpe mode, clear lp (bit 3) in mcgc2 to 0 here to switch to fbe mode e) fbe: loop until pllst (bit 5) in mcgsc is clear, indicating that the current source for the plls clock is the fll f) fbe: optionally, loop until lock (bit 6) in the mcgsc is set, indicating that the fll has acquired lock. although the fll is bypassed in fbe mode, it is still enabled and running. 3. next, fbe mode transitions into fbi mode: a) mcgc1 = 0x44 (%01000100) clks (bits7 and 6) in mcgsc1 set to %01 in order to switch the system clock to the internal reference clock irefs (bit 2) set to 1 to select the internal reference clock as the reference clock source rdiv (bits 5-3) set to %000, or divide-by-1 because the trimmed internal reference should be within the 31.25 khz to 39.0625 khz range required by the fll b) loop until irefst (bit 4) in mcgsc is 1, indicating the internal reference clock has been selected as the reference clock source c) loop until clkst (bits 3 and 2) in mcgsc are %01, indicating that the internal reference clock is selected to feed mcgout
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 158 freescale semiconductor 4. lastly, fbi transitions into blpi mode. a) mcgc2 = 0x08 (%00001000) lp (bit 3) in mcgsc is 1 figure 8-10. flowchart of pee to blpi mode transition using a 4 mhz crystal mcgc1 = $90 check clkst = %10 ? mcgc2 = $3e mcgc1 = $44 check irefst = 0? check clkst = %01? continue in blpi mode start in pee mode mcgc1 = $b8 mcgc3 = $04 enter blpe mode ? in blpe mode ? (lp=1) mcgc2 = $36 (lp = 0) check pllst = 0? optional: = 1? mcgc2 = $08 yes yes yes yes yes yes yes no no no no no no no check lock
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 159 8.5.2.3 example #3: moving from blpi to fee mode: external crystal = 4 mhz, bus frequency = 16 mhz in this example, the mcg will move through the proper operational modes from blpi mode at a 16 khz bus frequency running off of the internal reference clock (see previous example) to fee mode using a 4 mhz crystal con?ured for a 16 mhz bus frequency. first, the code sequence will be described. then a ?wchart will be included which illustrates the sequence. 1. first, blpi must transition to fbi mode. a) mcgc2 = 0x00 (%00000000) lp (bit 3) in mcgsc is 0 b) optionally, loop until lock (bit 6) in the mcgsc is set, indicating that the fll has acquired lock. although the fll is bypassed in fbi mode, it is still enabled and running. 2. next, fbi will transition to fee mode. a) mcgc2 = 0x36 (%00110110) range (bit 5) set to 1 because the frequency of 4 mhz is within the high frequency range hgo (bit 4) set to 1 to con?ure external oscillator for high gain operation erefs (bit 2) set to 1, because a crystal is being used erclken (bit 1) set to 1 to ensure the external reference clock is active b) loop until oscinit (bit 1) in mcgsc is 1, indicating the crystal selected by the erefs bit has been initialized. c) mcgc1 = 0x38 (%00111000) clks (bits 7 and 6) set to %00 in order to select the output of the fll as system clock source rdiv (bits 5-3) set to %111, or divide-by-128 because 4 mhz / 128 = 31.25 khz which is in the 31.25 khz to 39.0625 khz range required by the fll irefs (bit 1) cleared to 0, selecting the external reference clock d) loop until irefst (bit 4) in mcgsc is 0, indicating the external reference clock is the current source for the reference clock e) optionally, loop until lock (bit 6) in the mcgsc is set, indicating that the fll has reacquired lock. f) loop until clkst (bits 3 and 2) in mcgsc are %00, indicating that the output of the fll is selected to feed mcgout
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 160 freescale semiconductor figure 8-11. flowchart of blpi to fee mode transition using a 4 mhz crystal 8.5.2.4 example # 4: moving from fei to pee mode: external crystal = 8 mhz, bus frequency = 8 mhz in this example, the mcg will move through the proper operational modes from fei to pee mode until the 8 mhz crystal reference frequency is set to achieve a bus frequency of 8 mhz. this example is similar to example number one except that in this case the frequency of the external crystal is 8 mhz instead of 4 mhz. special consideration must be taken with this case since there is a period of time along the way from fei mode to pee mode where the fll operates based on a reference clock with a frequency that is greater than the maximum allowed for the fll. this occurs because with an 8 mhz mcgc2 = $36 check oscinit = 1 ? mcgc1 = $38 check irefst = 0? check clkst = %00? continue in fee mode start i n blpi mode yes yes no no no mcgc2 = $00 optional: check lock = 1? yes no yes optional: check lock = 1? yes no
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 161 external crystal and a maximum reference divider factor of 128, the resulting frequency of the reference clock for the fll is 62.5 khz (greater than the 39.0625 khz maximum allowed). care must be taken in the software to minimize the amount of time spent in this state where the fll is operating in this condition. the following code sequence describes how to move from fei mode to pee mode until the 8 mhz crystal reference frequency is set to achieve a bus frequency of 8 mhz. because the mcg is in fei mode out of reset, this example also shows how to initialize the mcg for pee mode out of reset. first, the code sequence will be described. then a ?wchart will be included which illustrates the sequence. 1. first, fei must transition to fbe mode: a) mcgc2 = 0x36 (%00110110) bdiv (bits 7 and 6) set to %00, or divide-by-1 range (bit 5) set to 1 because the frequency of 8 mhz is within the high frequency range hgo (bit 4) set to 1 to con?ure external oscillator for high gain operation erefs (bit 2) set to 1, because a crystal is being used erclken (bit 1) set to 1 to ensure the external reference clock is active b) loop until oscinit (bit 1) in mcgsc is 1, indicating the crystal selected by the erefs bit has been initialized. c) block interrupts (if applicable by setting the interrupt bit in the ccr). d) mcgc1 = 0xb8 (%10111000) clks (bits 7 and 6) set to %10 in order to select external reference clock as system clock source rdiv (bits 5-3) set to %111, or divide-by-128. note 8 mhz / 128 = 62.5 khz which is greater than the 31.25 khz to 39.0625 khz range required by the fll. therefore after the transition to fbe is complete, software must progress through to blpe mode immediately by setting the lp bit in mcgc2. irefs (bit 2) cleared to 0, selecting the external reference clock e) loop until irefst (bit 4) in mcgsc is 0, indicating the external reference is the current source for the reference clock f) loop until clkst (bits 3 and 2) in mcgsc are %10, indicating that the external reference clock is selected to feed mcgout 2. then, fbe mode transitions into blpe mode: a) mcgc2 = 0x3e (%00111110) lp (bit 3) in mcgc2 to 1 (blpe mode entered) note there must be no extra steps (including interrupts) between steps 1d and 2a. b) enable interrupts (if applicable by clearing the interrupt bit in the ccr).
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 162 freescale semiconductor c) mcgc1 = 0x98 (%10011000) rdiv (bits 5-3) set to %011, or divide-by-8 because 8 mhz / 8= 1 mhz which is in the 1 mhz to 2 mhz range required by the pll. in blpe mode, the con?uration of the rdiv does not matter because both the fll and pll are disabled. changing them only sets up the the dividers for pll usage in pbe mode d) mcgc3 = 0x44 (%01000100) plls (bit 6) set to 1, selects the pll. in blpe mode, changing this bit only prepares the mcg for pll usage in pbe mode vdiv (bits 3-0) set to %0100, or multiply-by-16 because 1 mhz reference * 16 = 16 mhz. in blpe mode, the con?uration of the vdiv bits does not matter because the pll is disabled. changing them only sets up the multiply value for pll usage in pbe mode e) loop until pllst (bit 5) in mcgsc is set, indicating that the current source for the plls clock is the pll 3. then, blpe mode transitions into pbe mode: a) clear lp (bit 3) in mcgc2 to 0 here to switch to pbe mode b) then loop until lock (bit 6) in mcgsc is set, indicating that the pll has acquired lock 4. last, pbe mode transitions into pee mode: a) mcgc1 = 0x18 (%00011000) clks (bits7 and 6) in mcgsc1 set to %00 in order to select the output of the pll as the system clock source b) loop until clkst (bits 3 and 2) in mcgsc are %11, indicating that the pll output is selected to feed mcgout in the current clock mode now, with an rdiv of divide-by-8, a bdiv of divide-by-1, and a vdiv of multiply-by-16, mcgout = [(8 mhz / 8) * 16] / 1 = 16 mhz, and the bus frequency is mcgout / 2, or 8 mhz
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 163 figure 8-12. flowchart of fei to pee mode transition using a 8 mhz crystal mcgc2 = $36 check oscinit = 1 ? mcgc1 = $b8 check irefst = 0? check clkst = %10? mcgc2 = $3e (lp = 1) mcgc1 = $98 mcgc3 = $44 mcgc2 = $36 (lp = 0) check pllst = 1? mcgc1 = $18 check lock = 1? check clkst = %11? continue in pee mode start i n fei mode yes yes yes yes yes yes no no no no no no
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 164 freescale semiconductor 8.5.3 calibrating the internal reference clock (irc) the irc is calibrated by writing to the mcgtrm register ?st, then using the ftrim bit to ne tune the frequency. we will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1ff, where the ftrim bit is the lsb. the trim value after a por is always 0x100 (mcgtrm = 0x80 and ftrim = 0). writing a larger value will decrease the frequency and smaller values will increase the frequency. the trim value is linear with the period, except that slight variations in wafer fab processing produce slight non-linearities between trim value and period. these non-linearities are why an iterative trimming approach to search for the best trim value is recommended. in example #5: internal reference clock trim this approach will be demonstrated. after a trim value has been found for a device, this value can be stored in flash memory to save the value. if power is removed from the device, the irc can easily be re-trimmed by copying the saved value from flash to the mcg registers. freescale identi?s recommended flash locations for storing the trim value for each mcu. consult the memory map in the data sheet for these locations. on devices that are factory trimmed, the factory trim value will be stored in these locations. 8.5.3.1 example #5: internal reference clock trim for applications that require a tight frequency tolerance, a trimming procedure is provided that will allow a very accurate internal clock source. this section outlines one example of trimming the internal oscillator. many other possible trimming procedures are valid and can be used. in the example below, the mcg trim will be calibrated for the 9-bit mcgtrm and ftrim collective value. this value will be referred to as trmval.
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 165 figure 8-13. trim procedure in this particular case, the mcu has been attached to a pcb and the entire assembly is undergoing ?al test with automated test equipment. a separate signal or message is provided to the mcu operating under user provided software control. the mcu initiates a trim procedure as outlined in figure 8-13 while the tester supplies a precision reference signal. if the intended bus frequency is near the maximum allowed for the device, it is recommended to trim using a reference divider value (rdiv setting) of twice the ?al value. after the trim procedure is complete, the reference divider can be restored. this will prevent accidental overshoot of the maximum clock frequency. initial conditions: 1) clock supplied from ate has 500 s duty period 2) mcg configured for internal reference with 8mhz bus start trim procedure continue case statement count > expected = 500 . measure incoming clock width trmval = $100 count < expected = 500 count = expected = 500 trmval = trmval = trmval - 256/ (2**n) trmval + 256/ (2**n) n = n + 1 (count = # of bus clocks / 8) (decreasing trmval increases the frequency) (increasing trmval decreases the frequency) no yes is n > 9? (running too slow) (running too fast) n=1 store mcgtrm and ftrim values in non-volatile memory
chapter 8 multi-purpose clock generator (s08mcgv1) mc9s08de60 series data sheet, rev. 3 166 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 167 chapter 9 analog comparator (s08acmpv3) 9.1 introduction the analog comparator module (acmp) provides a circuit for comparing two analog input voltages or for comparing one analog input voltage to an internal reference voltage. the comparator circuit is designed to operate across the full range of the supply voltage (rail-to-rail operation). all mc9s08de60 series mcus have two full function acmps in a 64-pin package. mcus in the 48-pin package have two acmps, but the output of acmp2 is not accessible. mcus in the 32-pin package contain one full function acmp. note mc9s08de60 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode. please ignore references to stop1. 9.1.1 acmp con?uration information when using the bandgap reference voltage for input to acmp+, the user must enable the bandgap buffer by setting bgbe =1 in spmsc1 see section 5.8.7, ?ystem power management status and control 1 register (spmsc1) .?for value of bandgap voltage reference see section a.6, ?c characteristics .
chapter 9 analog comparator (s08acmpv3) mc9s08de60 series data sheet, rev. 3 168 freescale semiconductor figure 9-1. mc9s08de60/32 block diagram emphasizing the acmp block and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k
chapter 9 analog comparator (s08acmpv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 169 9.1.2 features the acmp has the following features: full rail to rail supply operation. selectable interrupt on rising edge, falling edge, or either rising or falling edges of comparator output. option to compare to ?ed internal bandgap reference voltage. option to allow comparator output to be visible on a pin, acmpxo. 9.1.3 modes of operation this section de?es the acmp operation in wait, stop, and background debug modes. 9.1.3.1 acmp in wait mode the acmp continues to run in wait mode if enabled before executing the appropriate instruction. therefore, the acmp can be used to bring the mcu out of wait mode if the acmp interrupt is enabled (acie is set). for lowest possible current consumption, the acmp should be disabled by software if not required as an interrupt source during wait mode. 9.1.3.2 acmp in stop modes the acmp is disabled in all stop modes, regardless of the settings before executing the stop instruction. therefore, the acmp cannot be used as a wake up source from stop modes. during stop2 mode, the acmp module is fully powered down. upon wake-up from stop2 mode, the acmp module is in the reset state. during stop3 mode, clocks to the acmp module are halted. no registers are affected. in addition, the acmp comparator circuit enters a low-power state. no compare operation occurs while in stop3. if stop3 is exited with a reset, the acmp is put into its reset state. if stop3 is exited with an interrupt, the acmp continues from the state it was in when stop3 was entered. 9.1.3.3 acmp in active background mode when the microcontroller is in active background mode, the acmp continues to operate normally.
chapter 9 analog comparator (s08acmpv3) mc9s08de60 series data sheet, rev. 3 170 freescale semiconductor 9.1.4 block diagram the block diagram for the analog comparator module is shown figure 9-2 . figure 9-2. analog comparator (acmp) block diagram 9.2 external signal description the acmp has two analog input pins, acmpx+ and acmpx ? and one digital output pin acmpxo. each of these pins can accept an input voltage that varies across the full operating voltage range of the mcu. as shown in figure 9-2 , the acmpx- pin is connected to the inverting input of the comparator, and the acmpx+ pin is connected to the comparator non-inverting input if acbgs is a 0. as shown in figure 9-2 , the acmpxo pin can be enabled to drive an external pin. the signal properties of acmp are shown in table 9-1 . table 9-1. signal properties signal function i/o acmpx- inverting analog input to the acmp. (minus input) i acmpx+ non-inverting analog input to the acmp. (positive input) i acmpxo digital output of the acmp. o + - interrupt control internal reference acbgs internal bus status & control register acmod set acf acme acf acie acope comparator acmpx interrupt request acmpx+ acmpx- acmpxo
chapter 9 analog comparator (s08acmpv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 171 9.3 memory map/register de?ition the acmp includes one register: an 8-bit status and control register refer to the direct-page register summary in the memory section of this document for the absolute address assignments for the acmp register.this section refers to register and control bits only by their names and relative address offsets. some mcus may have more than one acmp, so register names include placeholder characters (x) to identify which acmp is being referenced. 9.3.1 acmpx status and control register (acmpxsc) acmpxsc contains the status ?g and control bits used to enable and con?ure the acmp. table 9-2. acmp register summary name 76543210 acmpxsc r acme acbgs acf acie aco acope acmod w 76543210 r acme acbgs acf acie aco acope acmod w reset: 0 0 0 0 0 0 0 0 figure 9-3. acmpx status and control register (acmpxsc) table 9-3. acmpxsc field descriptions field description 7 acme analog comparator module enable. enables the acmp module. 0 acmp not enabled 1 acmp is enabled 6 acbgs analog comparator bandgap select. selects between the bandgap reference voltage or the acmpx+ pin as the input to the non-inverting input of the analog comparator. 0 external pin acmpx+ selected as non-inverting input to comparator 1 internal reference select as non-inverting input to comparator 5 acf analog comparator flag. acf is set when a compare event occurs. compare events are de?ed by acmod. acf is cleared by writing a one to it. 0 compare event has not occurred 1 compare event has occurred 4 acie analog comparator interrupt enable. enables the interrupt from the acmp. when acie is set, an interrupt is asserted when acf is set. 0 interrupt disabled 1 interrupt enabled
chapter 9 analog comparator (s08acmpv3) mc9s08de60 series data sheet, rev. 3 172 freescale semiconductor 9.4 functional description the analog comparator can compare two analog input voltages applied to acmpx+ and acmpx ?, or it can compare an analog input voltage applied to acmpx ? with an internal bandgap reference voltage. acbgs selects between the bandgap reference voltage or the acmpx+ pin as the input to the non-inverting input of the analog comparator. the comparator output is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input. acmod selects the condition that causes acf to be set. acf can be set on a rising edge of the comparator output, a falling edge of the comparator output, or a rising or a falling edge (toggle). the comparator output can be read directly through aco. the comparator output can be driven onto the acmpxo pin using acope. 3 aco analog comparator output. reading aco returns the current value of the analog comparator output. aco is reset to a 0 and reads as a 0 when the acmp is disabled (acme = 0). 2 acope analog comparator output pin enable. enables the comparator output to be placed onto the external pin, acmpxo. 0 analog comparator output not available on acmpxo 1 analog comparator output is driven out on acmpxo 1:0 acmod analog comparator mode. acmod selects the type of compare event which sets acf. 00 encoding 0 ?comparator output falling edge 01 encoding 1 ?comparator output rising edge 10 encoding 2 ?comparator output falling edge 11 encoding 3 ?comparator output rising or falling edge table 9-3. acmpxsc field descriptions (continued) field description
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 173 chapter 10 analog-to-digital converter (s08adc12v1) 10.1 introduction the 12-bit analog-to-digital converter (adc) is a successive approximation adc designed for operation within an integrated microcontroller system-on-chip. note mc9s08de60 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode. please ignore references to stop1. 10.1.1 analog power and ground signal names references to v ddad and v ssad in this chapter correspond to signals v dda and v ssa , respectively. 10.1.2 channel assignments note the adc channel assignments for the mc9s08de60 series devices are shown in table 10-1 . reserved channels convert to an unknown value. this chapter shows bits for all s08adc12v1 channels. mc9s08de60 series mcus do not use all of these channels. all bits corresponding to channels that are not available on a device are reserved.
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 174 freescale semiconductor 10.1.3 alternate clock the adc module is capable of performing conversions using the mcu bus clock, the bus clock divided by two, the local asynchronous clock (adack) within the module, or the alternate clock, altclk. the alternate clock for the mc9s08de60 series mcu devices is the external reference clock (mcgerclk). the selected clock source must run at a frequency such that the adc conversion clock (adck) runs at a frequency within its speci?d range (f adck ) after being divided down from the altclk input as determined by the adiv bits. altclk is active while the mcu is in wait mode provided the conditions described above are met. this allows altclk to be used as the conversion clock source for the adc while the mcu is in wait mode. altclk cannot be used as the adc conversion clock source while the mcu is in either stop2 or stop3. 10.1.4 hardware trigger the adc hardware trigger, adhwt, is the output from the real time counter (rtc). the rtc counter can be clocked by either mcgerclk or a nominal 1 khz clock source. the period of the rtc is determined by the input clock frequency, the rtcps bits, and the rtcmod register. when the adc hardware trigger is enabled, a conversion is initiated upon an rtc counter over?w. the rtc can be con?ured to cause a hardware trigger in mcu run, wait, and stop3. table 10-1. adc channel assignment adch channel input 00000 ad0 pta0/adp0/mclk 00001 ad1 pta1/adp1/acmp1+ 00010 ad2 pta2/adp2/acmp1p- 00011 ad3 pta3/adp3/acmp1o 00100 ad4 pta4/adp4 00101 ad5 pta5/adp5 00110 ad6 pta6/adp6 00111 ad7 pta7/adp7 01000 ad8 ptb0/adp8 01001 ad9 ptb1/adp9 01010 ad10 ptb2/adp10 01011 ad11 ptb3/adp11 01100 ad12 ptb4/adp12 01101 ad13 ptb5/adp13 01110 ad14 ptb6/adp14 01111 ad15 ptb7/adp15 10000 ad16 ptc0/adp16 10001 ad17 ptc1/adp17 10010 ad18 ptc2/adp18 10011 ad19 ptc3/adp19 10100 ad20 ptc4/adp20 10101 ad21 ptc5/adp21 10110 ad22 ptc6/adp22 10111 ad23 ptc7/adp23 11000 ad24 through ad25 reserved 11001 11010 ad26 temperature sensor 1 11011 ad27 internal bandgap 2 11100 reserved reserved 11101 v refh v refh 11110 v v adch channel input
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 175 10.1.5 temperature sensor to use the on-chip temperature sensor, the user must perform the following: con?ure adc for long sample with a maximum of 1 mhz clock convert the bandgap voltage reference channel (ad27) by converting the digital value of the bandgap voltage reference channel using the value of v bg the user can determine v dd . for value of bandgap voltage, see section a.6, ?c characteristics? convert the temperature sensor channel (ad26) by using the calculated value of v dd , convert the digital value of ad26 into a voltage, v temp equation 10-1 provides an approximate transfer function of the temperature sensor. temp = 25 - ((v temp -v temp25 ) m) eqn. 10-1 where: ? temp is the voltage of the temperature sensor channel at the ambient temperature. ? temp25 is the voltage of the temperature sensor channel at 25 c. m is the hot or cold voltage versus temperature slope in v/ c. for temperature calculations, use the v temp25 and m values from the adc electricals table. in application code, the user reads the temperature sensor channel, calculates v temp , and compares to v temp25 .ifv temp is greater than v temp25 the cold slope value is applied in equation 10-1 .ifv temp is less than v temp25 the hot slope value is applied in equation 10-1 . to improve accuracy the user should calibrate the bandgap voltage reference and temperature sensor. calibrating at 25 c will improve accuracy to 4.5c. calibration at three points, -40c, 25c, and 125 c will improve accuracy to 2.5c. once calibration has been completed, the user will need to calculate the slope for both hot and cold. in application code, the user would then calculate the temperature using equation 10-1 as detailed above and then determine if the temperature is above or below 25 c. once determined if the temperature is above or below 25 c, the user can recalculate the temperature using the hot or cold slope value obtained during calibration.
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 176 freescale semiconductor figure 10-1. mc9s08de60/32 block diagram emphasizing the adc module and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 mc9s08dz32 = 32k
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 177 10.1.6 features features of the adc module include: linear successive approximation algorithm with 12-bit resolution up to 28 analog inputs output formatted in 12-, 10-, or 8-bit right-justi?d unsigned format single or continuous conversion (automatic return to idle after single conversion) con?urable sample time and conversion speed/power conversion complete ?g and interrupt input clock selectable from up to four sources operation in wait or stop3 modes for lower noise operation asynchronous clock source for lower noise operation selectable asynchronous hardware conversion trigger automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value temperature sensor 10.1.7 adc module block diagram figure 10-2 provides a block diagram of the adc module .
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 178 freescale semiconductor figure 10-2. adc block diagram 10.2 external signal description the adc module supports up to 28 separate analog inputs. it also requires four supply/reference/ground connections. table 10-2. signal properties name function ad27?d0 analog channel inputs v refh high reference voltage v refl low reference voltage v ddad analog power supply v ssad analog ground ad0 ?? ad27 v refh v refl advin adch control sequencer initialize sample convert transfer abort clock divide adck 2 async clock gen bus clock altclk adiclk adiv adack adco adlsmp adlpc mode complete data registers sar converter compare value registers compare value sum aien coco interrupt aien coco adtrg 1 2 1 2 mcu stop adhwt logic acfgt 3 compare true 3 compare true adccfg adcsc1 adcsc2
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 179 10.2.1 analog power (v ddad ) the adc analog portion uses v ddad as its power connection. in some packages, v ddad is connected internally to v dd . if externally available, connect the v ddad pin to the same voltage potential as v dd . external ?tering may be necessary to ensure clean v ddad for good results. 10.2.2 analog ground (v ssad ) the adc analog portion uses v ssad as its ground connection. in some packages, v ssad is connected internally to v ss . if externally available, connect the v ssad pin to the same voltage potential as v ss . 10.2.3 voltage reference high (v refh ) v refh is the high reference voltage for the converter. in some packages, v refh is connected internally to v ddad . if externally available, v refh may be connected to the same potential as v ddad or may be driven by an external source between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). 10.2.4 voltage reference low (v refl ) v refl is the low-reference voltage for the converter. in some packages, v refl is connected internally to v ssad . if externally available, connect the v refl pin to the same voltage potential as v ssad . 10.2.5 analog channel inputs (adx) the adc module supports up to 28 separate analog inputs. an input is selected for conversion through the adch channel select bits. 10.3 register de?ition these memory-mapped registers control and monitor operation of the adc: status and control register, adcsc1 status and control register, adcsc2 data result registers, adcrh and adcrl compare value registers, adccvh and adccvl con?uration register, adccfg pin control registers, apctl1, apctl2, apctl3 10.3.1 status and control register 1 (adcsc1) this section describes the function of the adc status and control register (adcsc1). writing adcsc1 aborts the current conversion and initiates a new conversion (if the adch bits are equal to a value other than all 1s).
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 180 freescale semiconductor 7654 3 210 r coco aien adco adch w reset: 0 0 0 1 1 1 1 1 figure 10-3. status and control register (adcsc1) table 10-3. adcsc1 field descriptions field description 7 coco conversion complete flag. the coco ?g is a read-only bit set each time a conversion is completed when the compare function is disabled (acfe = 0). when the compare function is enabled (acfe = 1), the coco ?g is set upon completion of a conversion only if the compare result is true. this bit is cleared when adcsc1 is written or when adcrl is read. 0 conversion not completed 1 conversion completed 6 aien interrupt enable aien enables conversion complete interrupts. when coco becomes set while aien is high, an interrupt is asserted. 0 conversion complete interrupt disabled 1 conversion complete interrupt enabled 5 adco continuous conversion enable. adco enables continuous conversions. 0 one conversion following a write to the adcsc1 when software triggered operation is selected, or one conversion following assertion of adhwt when hardware triggered operation is selected. 1 continuous conversions initiated following a write to adcsc1 when software triggered operation is selected. continuous conversions are initiated by an adhwt event when hardware triggered operation is selected. 4:0 adch input channel select. the adch bits form a 5-bit ?ld that selects one of the input channels. the input channels are detailed in table 10-4 . the successive approximation converter subsystem is turned off when the channel select bits are all set. this feature allows for explicit disabling of the adc and isolation of the input channel from all sources. terminating continuous conversions this way prevents an additional, single conversion from being performed. it is not necessary to set the channel select bits to all ones to place the adc in a low-power state when continuous conversions are not enabled because the module automatically enters a low-power state when a conversion completes. table 10-4. input channel select adch input select 00000?1111 ad0?5 10000?1011 ad16?7 11100 reserved 11101 v refh 11110 v refl 11111 module disabled
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 181 10.3.2 status and control register 2 (adcsc2) the adcsc2 register controls the compare function, conversion trigger, and conversion active of the adc module. 10.3.3 data result high register (adcrh) in 12-bit operation, adcrh contains the upper four bits of the result of a 12-bit conversion. in 10-bit mode, adcrh contains the upper two bits of the result of a 10-bit conversion. when con?ured for 10-bit mode, adr[11:10] are cleared. when con?ured for 8-bit mode, adr[11:8] are cleared. in 12-bit and 10-bit mode, adcrh is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. when a compare event does occur, the value is the addition of the conversion result and the twos complement of the compare value. in 12-bit and 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until after the next conversion is completed, the intermediate conversion result is lost. in 8-bit mode, there is no interlocking with adcrl. 7654 3 210 reset: 0 0 0 0 0 0 0 0 figure 10-4. status and control register 2 (adcsc2) table 10-5. adcsc2 register field descriptions field description 7 adact conversion active. indicates that a conversion is in progress. adact is set when a conversion is initiated and cleared when a conversion is completed or aborted. 0 conversion not in progress 1 conversion in progress 6 adtrg conversion trigger select. selects the type of trigger used for initiating a conversion. two types of triggers are selectable: software trigger and hardware trigger. when software trigger is selected, a conversion is initiated following a write to adcsc1. when hardware trigger is selected, a conversion is initiated following the assertion of the adhwt input. 0 software trigger selected 1 hardware trigger selected 5 acfe compare function enable. enables the compare function. 0 compare function disabled 1 compare function enabled 4 acfgt compare function greater than enable. con?ures the compare function to trigger when the result of the conversion of the input being monitored is greater than or equal to the compare value. the compare function defaults to triggering when the result of the compare of the input being monitored is less than the compare value. 0 compare triggers when input is less than compare value 1 compare triggers when input is greater than or equal to compare value
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 182 freescale semiconductor if the mode bits are changed, any data in adcrh becomes invalid. 10.3.4 data result low register (adcrl) adcrl contains the lower eight bits of the result of a 12-bit or 10-bit conversion, and all eight bits of an 8-bit conversion. this register is updated each time a conversion completes except when automatic compare is enabled and the compare condition is not met. when a compare event does occur, the value is the addition of the conversion result and the twos complement of the compare value. in 12-bit and 10-bit mode, reading adcrh prevents the adc from transferring subsequent conversion results into the result registers until adcrl is read. if adcrl is not read until the after next conversion is completed, the intermediate conversion results are lost. in 8-bit mode, there is no interlocking with adcrh. if the mode bits are changed, any data in adcrl becomes invalid. 10.3.5 compare value high register (adccvh) in 12-bit mode, the adccvh register holds the upper four bits of the 12-bit compare value. when the compare function is enabled, these bits are compared to the upper four bits of the result following a conversion in 12-bit mode. 7654 3 210 r 0 0 0 0 adr11 adr10 adr9 adr8 w reset: 0 0 0 0 0 0 0 0 figure 10-5. data result high register (adcrh) 7654 3 210 r adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 w reset: 0 0 0 0 0 0 0 0 figure 10-6. data result low register (adcrl) 7654 3 210 r0000 adcv11 adcv10 adcv9 adcv8 w reset: 0 0 0 0 0 0 0 0 figure 10-7. compare value high register (adccvh)
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 183 in 10-bit mode, the adccvh register holds the upper two bits of the 10-bit compare value (adcv[9:8]). these bits are compared to the upper two bits of the result following a conversion in 10-bit mode when the compare function is enabled. in 8-bit mode, adccvh is not used during compare. 10.3.6 compare value low register (adccvl) this register holds the lower 8 bits of the 12-bit or 10-bit compare value or all 8 bits of the 8-bit compare value. when the compare function is enabled, bits adcv[7:0] are compared to the lower 8 bits of the result following a conversion in 12-bit, 10-bit or 8-bit mode. 10.3.7 con?uration register (adccfg) adccfg selects the mode of operation, clock source, clock divide, and con?ures for low power and long sample time. 7654 3 210 r adcv7 adcv6 adcv5 adcv4 adcv3 adcv2 adcv1 adcv0 w reset: 0 0 0 0 0 0 0 0 figure 10-8. compare value low register (adccvl) 7654 3 210 r adlpc adiv adlsmp mode adiclk w reset: 0 0 0 0 0 0 0 0 figure 10-9. con?uration register (adccfg) table 10-6. adccfg register field descriptions field description 7 adlpc low-power con?uration. adlpc controls the speed and power con?uration of the successive approximation converter. this optimizes power consumption when higher sample rates are not required. 0 high speed con?uration 1 low power con?uration: the power is reduced at the expense of maximum clock speed. 6:5 adiv clock divide select. adiv selects the divide ratio used by the adc to generate the internal clock adck. table 10-7 shows the available clock con?urations. 4 adlsmp long sample time con?uration. adlsmp selects between long and short sample time. this adjusts the sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion speed for lower impedance inputs. longer sample times can also be used to lower overall power consumption when continuous conversions are enabled if high conversion rates are not required. 0 short sample time 1 long sample time
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 184 freescale semiconductor 10.3.8 pin control 1 register (apctl1) the pin control registers disable the i/o port control of mcu pins used as analog inputs. apctl1 is 3:2 mode conversion mode selection. mode bits are used to select between 12-, 10-, or 8-bit operation. see table 10-8 . 1:0 adiclk input clock select. adiclk bits select the input clock source to generate the internal clock adck. see table 10-9 . table 10-7. clock divide select adiv divide ratio clock rate 00 1 input clock 01 2 input clock 2 10 4 input clock 4 11 8 input clock 8 table 10-8. conversion modes mode mode description 00 8-bit conversion (n=8) 01 12-bit conversion (n=12) 10 10-bit conversion (n=10) 11 reserved table 10-9. input clock select adiclk selected clock source 00 bus clock 01 bus clock divided by 2 10 alternate clock (altclk) 11 asynchronous clock (adack) table 10-6. adccfg register field descriptions (continued) field description
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 185 used to control the pins associated with channels 0? of the adc module. 10.3.9 pin control 2 register (apctl2) apctl2 controls channels 8?5 of the adc module. 7654 3 210 r adpc7 adpc6 adpc5 adpc4 adpc3 adpc2 adpc1 adpc0 w reset: 0 0 0 0 0 0 0 0 figure 10-10. pin control 1 register (apctl1) table 10-10. apctl1 register field descriptions field description 7 adpc7 adc pin control 7. adpc7 controls the pin associated with channel ad7. 0 ad7 pin i/o control enabled 1 ad7 pin i/o control disabled 6 adpc6 adc pin control 6. adpc6 controls the pin associated with channel ad6. 0 ad6 pin i/o control enabled 1 ad6 pin i/o control disabled 5 adpc5 adc pin control 5. adpc5 controls the pin associated with channel ad5. 0 ad5 pin i/o control enabled 1 ad5 pin i/o control disabled 4 adpc4 adc pin control 4. adpc4 controls the pin associated with channel ad4. 0 ad4 pin i/o control enabled 1 ad4 pin i/o control disabled 3 adpc3 adc pin control 3. adpc3 controls the pin associated with channel ad3. 0 ad3 pin i/o control enabled 1 ad3 pin i/o control disabled 2 adpc2 adc pin control 2. adpc2 controls the pin associated with channel ad2. 0 ad2 pin i/o control enabled 1 ad2 pin i/o control disabled 1 adpc1 adc pin control 1. adpc1 controls the pin associated with channel ad1. 0 ad1 pin i/o control enabled 1 ad1 pin i/o control disabled 0 adpc0 adc pin control 0. adpc0 controls the pin associated with channel ad0. 0 ad0 pin i/o control enabled 1 ad0 pin i/o control disabled 7654 3 210 r adpc15 adpc14 adpc13 adpc12 adpc11 adpc10 adpc9 adpc8 w reset: 0 0 0 0 0 0 0 0 figure 10-11. pin control 2 register (apctl2)
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 186 freescale semiconductor 10.3.10 pin control 3 register (apctl3) apctl3 controls channels 16?3 of the adc module. table 10-11. apctl2 register field descriptions field description 7 adpc15 adc pin control 15. adpc15 controls the pin associated with channel ad15. 0 ad15 pin i/o control enabled 1 ad15 pin i/o control disabled 6 adpc14 adc pin control 14. adpc14 controls the pin associated with channel ad14. 0 ad14 pin i/o control enabled 1 ad14 pin i/o control disabled 5 adpc13 adc pin control 13. adpc13 controls the pin associated with channel ad13. 0 ad13 pin i/o control enabled 1 ad13 pin i/o control disabled 4 adpc12 adc pin control 12. adpc12 controls the pin associated with channel ad12. 0 ad12 pin i/o control enabled 1 ad12 pin i/o control disabled 3 adpc11 adc pin control 11. adpc11 controls the pin associated with channel ad11. 0 ad11 pin i/o control enabled 1 ad11 pin i/o control disabled 2 adpc10 adc pin control 10. adpc10 controls the pin associated with channel ad10. 0 ad10 pin i/o control enabled 1 ad10 pin i/o control disabled 1 adpc9 adc pin control 9. adpc9 controls the pin associated with channel ad9. 0 ad9 pin i/o control enabled 1 ad9 pin i/o control disabled 0 adpc8 adc pin control 8. adpc8 controls the pin associated with channel ad8. 0 ad8 pin i/o control enabled 1 ad8 pin i/o control disabled 7654 3 210 r adpc23 adpc22 adpc21 adpc20 adpc19 adpc18 adpc17 adpc16 w reset: 0 0 0 0 0 0 0 0 figure 10-12. pin control 3 register (apctl3)
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 187 10.4 functional description the adc module is disabled during reset or when the adch bits are all high. the module is idle when a conversion has completed and another conversion has not been initiated. when idle, the module is in its lowest power state. the adc can perform an analog-to-digital conversion on any of the software selectable channels. in 12-bit and 10-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 12-bit digital result. in 8-bit mode, the selected channel voltage is converted by a successive approximation algorithm into a 9-bit digital result. when the conversion is completed, the result is placed in the data registers (adcrh and adcrl). in 10-bit mode, the result is rounded to 10 bits and placed in the data registers (adcrh and adcrl). in 8-bit mode, the result is rounded to 8 bits and placed in adcrl. the conversion complete ?g (coco) is then set and an interrupt is generated if the conversion complete interrupt has been enabled (aien = 1). the adc module has the capability of automatically comparing the result of a conversion with the contents of its compare registers. the compare function is enabled by setting the acfe bit and operates with any of the conversion modes and con?urations. table 10-12. apctl3 register field descriptions field description 7 adpc23 adc pin control 23. adpc23 controls the pin associated with channel ad23. 0 ad23 pin i/o control enabled 1 ad23 pin i/o control disabled 6 adpc22 adc pin control 22. adpc22 controls the pin associated with channel ad22. 0 ad22 pin i/o control enabled 1 ad22 pin i/o control disabled 5 adpc21 adc pin control 21. adpc21 controls the pin associated with channel ad21. 0 ad21 pin i/o control enabled 1 ad21 pin i/o control disabled 4 adpc20 adc pin control 20. adpc20 controls the pin associated with channel ad20. 0 ad20 pin i/o control enabled 1 ad20 pin i/o control disabled 3 adpc19 adc pin control 19. adpc19 controls the pin associated with channel ad19. 0 ad19 pin i/o control enabled 1 ad19 pin i/o control disabled 2 adpc18 adc pin control 18. adpc18 controls the pin associated with channel ad18. 0 ad18 pin i/o control enabled 1 ad18 pin i/o control disabled 1 adpc17 adc pin control 17. adpc17 controls the pin associated with channel ad17. 0 ad17 pin i/o control enabled 1 ad17 pin i/o control disabled 0 adpc16 adc pin control 16. adpc16 controls the pin associated with channel ad16. 0 ad16 pin i/o control enabled 1 ad16 pin i/o control disabled
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 188 freescale semiconductor 10.4.1 clock select and divide control one of four clock sources can be selected as the clock source for the adc module. this clock source is then divided by a con?urable value to generate the input clock to the converter (adck). the clock is selected from one of the following sources by means of the adiclk bits. the bus clock, which is equal to the frequency at which software is executed. this is the default selection following reset. the bus clock divided by two. for higher bus clock rates, this allows a maximum divide by 16 of the bus clock. altclk, as de?ed for this mcu (see module section introduction). the asynchronous clock (adack). this clock is generated from a clock source within the adc module. when selected as the clock source, this clock remains active while the mcu is in wait or stop3 mode and allows conversions in these modes for lower noise operation. whichever clock is selected, its frequency must fall within the speci?d frequency range for adck. if the available clocks are too slow, the adc do not perform according to speci?ations. if the available clocks are too fast, the clock must be divided to the appropriate frequency. this divider is speci?d by the adiv bits and can be divide-by 1, 2, 4, or 8. 10.4.2 input select and pin control the pin control registers (apctl3, apctl2, and apctl1) disable the i/o port control of the pins used as analog inputs.when a pin control register bit is set, the following conditions are forced for the associated mcu pin: the output buffer is forced to its high impedance state. the input buffer is disabled. a read of the i/o port returns a zero for any pin with its input buffer disabled. the pullup is disabled. 10.4.3 hardware trigger the adc module has a selectable asynchronous hardware conversion trigger, adhwt, that is enabled when the adtrg bit is set. this source is not available on all mcus. consult the module introduction for information on the adhwt source speci? to this mcu. when adhwt source is available and hardware trigger is enabled (adtrg=1), a conversion is initiated on the rising edge of adhwt. if a conversion is in progress when a rising edge occurs, the rising edge is ignored. in continuous convert con?uration, only the initial rising edge to launch continuous conversions is observed. the hardware trigger function operates in conjunction with any of the conversion modes and con?urations. 10.4.4 conversion control conversions can be performed in 12-bit mode, 10-bit mode, or 8-bit mode as determined by the mode bits. conversions can be initiated by a software or hardware trigger. in addition, the adc module can be
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 189 con?ured for low power operation, long sample time, continuous conversion, and automatic compare of the conversion result to a software determined compare value. 10.4.4.1 initiating conversions a conversion is initiated: following a write to adcsc1 (with adch bits not all 1s) if software triggered operation is selected. following a hardware trigger (adhwt) event if hardware triggered operation is selected. following the transfer of the result to the data registers when continuous conversion is enabled. if continuous conversions are enabled, a new conversion is automatically initiated after the completion of the current conversion. in software triggered operation, continuous conversions begin after adcsc1 is written and continue until aborted. in hardware triggered operation, continuous conversions begin after a hardware trigger event and continue until aborted. 10.4.4.2 completing conversions a conversion is completed when the result of the conversion is transferred into the data result registers, adcrh and adcrl. this is indicated by the setting of coco. an interrupt is generated if aien is high at the time that coco is set. a blocking mechanism prevents a new result from overwriting previous data in adcrh and adcrl if the previous data is in the process of being read while in 12-bit or 10-bit mode (the adcrh register has been read but the adcrl register has not). when blocking is active, the data transfer is blocked, coco is not set, and the new result is lost. in the case of single conversions with the compare function enabled and the compare condition false, blocking has no effect and adc operation is terminated. in all other cases of operation, when a data transfer is blocked, another conversion is initiated regardless of the state of adco (single or continuous conversions enabled). if single conversions are enabled, the blocking mechanism could result in several discarded conversions and excess power consumption. to avoid this issue, the data registers must not be read after initiating a single conversion until the conversion completes. 10.4.4.3 aborting conversions any conversion in progress is aborted when: a write to adcsc1 occurs (the current conversion will be aborted and a new conversion will be initiated, if adch are not all 1s). a write to adcsc2, adccfg, adccvh, or adccvl occurs. this indicates a mode of operation change has occurred and the current conversion is therefore invalid. the mcu is reset. the mcu enters stop mode with adack not enabled.
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 190 freescale semiconductor when a conversion is aborted, the contents of the data registers, adcrh and adcrl, are not altered. however, they continue to be the values transferred after the completion of the last successful conversion. if the conversion was aborted by a reset, adcrh and adcrl return to their reset states. 10.4.4.4 power control the adc module remains in its idle state until a conversion is initiated. if adack is selected as the conversion clock source, the adack clock generator is also enabled. power consumption when active can be reduced by setting adlpc. this results in a lower maximum value for f adck (see the electrical speci?ations). 10.4.4.5 sample time and total conversion time the total conversion time depends on the sample time (as determined by adlsmp), the mcu bus frequency, the conversion mode (8-bit, 10-bit or 12-bit), and the frequency of the conversion clock ( f adck ). after the module becomes active, sampling of the input begins. adlsmp selects between short (3.5 adck cycles) and long (23.5 adck cycles) sample times.when sampling is complete, the converter is isolated from the input channel and a successive approximation algorithm is performed to determine the digital value of the analog signal. the result of the conversion is transferred to adcrh and adcrl upon completion of the conversion algorithm. if the bus frequency is less than the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when short sample is enabled (adlsmp=0). if the bus frequency is less than 1/11th of the f adck frequency, precise sample time for continuous conversions cannot be guaranteed when long sample is enabled (adlsmp=1). the maximum total conversion time for different conditions is summarized in table 10-13 . table 10-13. total conversion time vs. control conditions conversion type adiclk adlsmp max total conversion time single or ?st continuous 8-bit 0x, 10 0 20 adck cycles + 5 bus clock cycles single or ?st continuous 10-bit or 12-bit 0x, 10 0 23 adck cycles + 5 bus clock cycles single or ?st continuous 8-bit 0x, 10 1 40 adck cycles + 5 bus clock cycles single or ?st continuous 10-bit or 12-bit 0x, 10 1 43 adck cycles + 5 bus clock cycles single or ?st continuous 8-bit 11 0 5 s + 20 adck + 5 bus clock cycles single or ?st continuous 10-bit or 12-bit 11 0 5 s + 23 adck + 5 bus clock cycles single or ?st continuous 8-bit 11 1 5 s + 40 adck + 5 bus clock cycles single or ?st continuous 10-bit or 12-bit 11 1 5 s + 43 adck + 5 bus clock cycles subsequent continuous 8-bit; f bus > f adck xx 0 17 adck cycles subsequent continuous 10-bit or 12-bit; f bus > f adck xx 0 20 adck cycles subsequent continuous 8-bit; f bus > f adck /11 xx 1 37 adck cycles
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 191 the maximum total conversion time is determined by the clock source chosen and the divide ratio selected. the clock source is selectable by the adiclk bits, and the divide ratio is speci?d by the adiv bits. for example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1 ratio selected, and a bus frequency of 8 mhz, then the conversion time for a single conversion is: note the adck frequency must be between f adck minimum and f adck maximum to meet adc speci?ations. 10.4.5 automatic compare function the compare function can be con?ured to check for an upper or lower limit. after the input is sampled and converted, the result is added to the twos complement of the compare value (adccvh and adccvl). when comparing to an upper limit (acfgt = 1), if the result is greater-than or equal-to the compare value, coco is set. when comparing to a lower limit (acfgt = 0), if the result is less than the compare value, coco is set. the value generated by the addition of the conversion result and the twos complement of the compare value is transferred to adcrh and adcrl. upon completion of a conversion while the compare function is enabled, if the compare condition is not true, coco is not set and no data is transferred to the result registers. an adc interrupt is generated upon the setting of coco if the adc interrupt is enabled (aien = 1). note the compare function can monitor the voltage on a channel while the mcu is in wait or stop3 mode. the adc interrupt wakes the mcu when the compare condition is met. 10.4.6 mcu wait mode operation wait mode is a lower power-consumption standby mode from which recovery is fast because the clock sources remain active. if a conversion is in progress when the mcu enters wait mode, it continues until completion. conversions can be initiated while the mcu is in wait mode by means of the hardware trigger or if continuous conversions are enabled. the bus clock, bus clock divided by two, and adack are available as conversion clock sources while in wait mode. the use of altclk as the conversion clock source in wait is dependent on the de?ition of subsequent continuous 10-bit or 12-bit; f bus > f adck /11 xx 1 40 adck cycles table 10-13. total conversion time vs. control conditions conversion type adiclk adlsmp max total conversion time 23 adck cyc conversion time = 8 mhz/1 number of bus cycles = 3.5 ms x 8 mhz = 28 cycles 5 bus cyc 8 mhz + = 3.5 ms
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 192 freescale semiconductor altclk for this mcu. consult the module introduction for information on altclk speci? to this mcu. a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from wait mode if the adc interrupt is enabled (aien = 1). 10.4.7 mcu stop3 mode operation stop mode is a low power-consumption standby mode during which most or all clock sources on the mcu are disabled. 10.4.7.1 stop3 mode with adack disabled if the asynchronous clock, adack, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the adc in its idle state. the contents of adcrh and adcrl are unaffected by stop3 mode. after exiting from stop3 mode, a software or hardware trigger is required to resume conversions. 10.4.7.2 stop3 mode with adack enabled if adack is selected as the conversion clock, the adc continues operation during stop3 mode. for guaranteed adc operation, the mcus voltage regulator must remain active during stop3 mode. consult the module introduction for con?uration information for this mcu. if a conversion is in progress when the mcu enters stop3 mode, it continues until completion. conversions can be initiated while the mcu is in stop3 mode by means of the hardware trigger or if continuous conversions are enabled. a conversion complete event sets the coco and generates an adc interrupt to wake the mcu from stop3 mode if the adc interrupt is enabled (aien = 1). note the adc module can wake the system from low-power stop and cause the mcu to begin consuming run-level currents without generating a system level interrupt. to prevent this scenario, software should ensure the data transfer blocking mechanism (discussed in section 10.4.4.2, ?ompleting conversions ) is cleared when entering stop3 and continuing adc conversions. 10.4.8 mcu stop2 mode operation the adc module is automatically disabled when the mcu enters stop2 mode. all module registers contain their reset values following exit from stop2. therefore, the module must be re-enabled and re-con?ured following exit from stop2.
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 193 10.5 initialization information this section gives an example that provides some basic direction on how to initialize and con?ure the adc module. you can con?ure the module for 8-, 10-, or 12-bit resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. refer to table 10-7 , table 10-8 , and table 10-9 for information used in this example. note hexadecimal values designated by a preceding 0x, binary values designated by a preceding %, and decimal values have no preceding character. 10.5.1 adc module initialization example 10.5.1.1 initialization sequence before the adc module can be used to complete conversions, an initialization procedure must be performed. a typical sequence is as follows: 1. update the con?uration register (adccfg) to select the input clock source and the divide ratio used to generate the internal clock, adck. this register is also used for selecting sample time and low-power con?uration. 2. update status and control register 2 (adcsc2) to select the conversion trigger (hardware or software) and compare function options, if enabled. 3. update status and control register 1 (adcsc1) to select whether conversions will be continuous or completed only once, and to enable or disable conversion complete interrupts. the input channel on which conversions will be performed is also selected here. 10.5.1.2 pseudo-code example in this example, the adc module is set up with interrupts enabled to perform a single 10-bit conversion at low power with a long sample time on input channel 1, where the internal adck clock is derived from the bus clock divided by 1. adccfg = 0x98 (%10011000) bit 7 adlpc 1 configures for low power (lowers maximum clock speed) bit 6:5 adiv 00 sets the adck to the input clock 1 bit 4 adlsmp 1 configures for long sample time bit 3:2 mode 10 sets mode at 10-bit conversions bit 1:0 adiclk 00 selects bus clock as input clock source adcsc2 = 0x00 (%00000000) bit 7 adact 0 flag indicates if a conversion is in progress bit 6 adtrg 0 software trigger selected bit 5 acfe 0 compare function disabled bit 4 acfgt 0 not used in this example bit 3:2 00 reserved, always reads zero bit 1:0 00 reserved for freescale? internal use; always write zero
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 194 freescale semiconductor adcsc1 = 0x41 (%01000001) bit 7 coco 0 read-only flag which is set when a conversion completes bit 6 aien 1 conversion complete interrupt enabled bit 5 adco 0 one conversion only (continuous conversions disabled) bit 4:0 adch 00001 input channel 1 selected as adc input channel adcrh/l = 0xxx holds results of conversion. read high byte (adcrh) before low byte (adcrl) so that conversion data cannot be overwritten with data from the next conversion. adccvh/l = 0xxx holds compare value when compare function enabled apctl1=0x02 ad1 pin i/o control disabled. all other ad pins remain general purpose i/o pins apctl2=0x00 all other ad pins remain general purpose i/o pins figure 10-13. initialization flowchart for example ye s no reset initialize adc adccfg = 0x98 adcsc1 = 0x41 adcsc2 = 0x00 check coco=1? read adcrh then adcrl to clear coco bit continue
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 195 10.6 application information this section contains information for using the adc module in applications. the adc has been designed to be integrated into a microcontroller for use in embedded control applications requiring an a/d converter. 10.6.1 external pins and routing the following sections discuss the external pins associated with the adc module and how they should be used for best results. 10.6.1.1 analog supply pins the adc module has analog power and ground supplies (v ddad and v ssad ) available as separate pins on some devices. v ssad is shared on the same pin as the mcu digital v ss on some devices. on other devices, v ssad and v ddad are shared with the mcu digital supply pins. in these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained. when available on a separate pin, both v ddad and v ssad must be connected to the same voltage potential as their corresponding mcu digital supply (v dd and v ss ) and must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. if separate power supplies are used for analog and digital power, the ground connection between these supplies must be at the v ssad pin. this should be the only ground connection between these supplies if possible. the v ssad pin makes a good single point ground location. 10.6.1.2 analog reference pins in addition to the analog supplies, the adc module has connections for two reference voltage inputs. the high reference is v refh , which may be shared on the same pin as v ddad on some devices. the low reference is v refl , which may be shared on the same pin as v ssad on some devices. when available on a separate pin, v refh may be connected to the same potential as v ddad , or may be driven by an external source between the minimum v ddad spec and the v ddad potential (v refh must never exceed v ddad ). when available on a separate pin, v refl must be connected to the same voltage potential as v ssad .v refh and v refl must be routed carefully for maximum noise immunity and bypass capacitors placed as near as possible to the package. ac current in the form of current spikes required to supply charge to the capacitor array at each successive approximation step is drawn through the v refh and v refl loop. the best external component to meet this current demand is a 0.1 f capacitor with good high frequency characteristics. this capacitor is connected between v refh and v refl and must be placed as near as possible to the package pins. resistance in the path is not recommended because the current causes a voltage drop that could result in conversion errors. inductance in this path must be minimum (parasitic only).
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 196 freescale semiconductor 10.6.1.3 analog input pins the external analog inputs are typically shared with digital i/o pins on mcu devices. the pin i/o control is disabled by setting the appropriate control bit in one of the pin control registers. conversions can be performed on inputs without the associated pin control register bit set. it is recommended that the pin control register bit always be set when using a pin as an analog input. this avoids problems with contention because the output buffer is in its high impedance state and the pullup is disabled. also, the input buffer draws dc current when its input is not at v dd or v ss . setting the pin control register bits for all pins used as analog inputs should be done to achieve lowest operating current. empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. use of 0.01 f capacitors with good high-frequency characteristics is suf?ient. these capacitors are not necessary in all cases, but when used they must be placed as near as possible to the package pins and be referenced to v ssa . for proper conversion, the input voltage must fall between v refh and v refl . if the input is equal to or exceeds v refh , the converter circuit converts the signal to 0xfff (full scale 12-bit representation), 0x3ff (full scale 10-bit representation) or 0xff (full scale 8-bit representation). if the input is equal to or less than v refl , the converter circuit converts it to 0x000. input voltages between v refh and v refl are straight-line linear conversions. there is a brief current associated with v refl when the sampling capacitor is charging. the input is sampled for 3.5 cycles of the adck source when adlsmp is low, or 23.5 cycles when adlsmp is high. for minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be transitioning during conversions. 10.6.2 sources of error several sources of error exist for a/d conversions. these are discussed in the following sections. 10.6.2.1 sampling error for proper conversions, the input must be sampled long enough to achieve the proper accuracy. given the maximum input resistance of approximately 7k and input capacitance of approximately 5.5 pf, sampling to within 1/4 lsb (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @ 8 mhz maximum adck frequency) provided the resistance of the external analog source (r as ) is kept below 2 k . higher source resistances or higher-accuracy sampling is possible by setting adlsmp (to increase the sample window to 23.5 cycles) or decreasing adck frequency to increase sample time. 10.6.2.2 pin leakage error leakage on the i/o pins can cause conversion error if the external analog source resistance (r as ) is high. if this error cannot be tolerated by the application, keep r as lower than v ddad /(2 n *i leak ) for less than 1/4 lsb leakage error (n = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 197 10.6.2.3 noise-induced errors system noise that occurs during the sample or conversion process can affect the accuracy of the conversion. the adc accuracy numbers are guaranteed as speci?d only if the following conditions are met: there is a 0.1 f low-esr capacitor from v refh to v refl . there is a 0.1 f low-esr capacitor from v ddad to v ssad . if inductive isolation is used from the primary supply, an additional 1 f capacitor is placed from v ddad to v ssad . ? ssad (and v refl , if connected) is connected to v ss at a quiet point in the ground plane. operate the mcu in wait or stop3 mode before initiating (hardware triggered conversions) or immediately after initiating (hardware or software triggered conversions) the adc conversion. for software triggered conversions, immediately follow the write to adcsc1 with a wait instruction or stop instruction. for stop3 mode operation, select adack as the clock source. operation in stop3 reduces v dd noise but increases effective conversion time due to stop recovery. there is no i/o switching, input or output, on the mcu during the conversion. there are some situations where external system activity causes radiated or conducted noise emissions or excessive v dd noise is coupled into the adc. in these situations, or when the mcu cannot be placed in wait or stop3 or i/o activity cannot be halted, these recommended actions may reduce the effect of noise on the accuracy: place a 0.01 f capacitor (c as ) on the selected input channel to v refl or v ssad (this improves noise issues, but affects the sample rate based on the external analog source resistance). average the result by converting the analog input many times in succession and dividing the sum of the results. four samples are required to eliminate the effect of a 1 lsb , one-time error. reduce the effect of synchronous noise by operating off the asynchronous clock (adack) and averaging. noise that is synchronous to adck cannot be averaged out. 10.6.2.4 code width and quantization error the adc quantizes the ideal straight-line transfer function into 4096 steps (in 12-bit mode). each step ideally has the same height (1 code) and width. the width is de?ed as the delta between the transition points to one code and the next. the ideal code width for an n bit converter (in this case n can be 8, 10 or 12), de?ed as 1 lsb , is: 1 lsb = (v refh - v refl ) / 2 n eqn. 10-2 there is an inherent quantization error due to the digitization of the result. for 8-bit or 10-bit conversions the code transitions when the voltage is at the midpoint between the points where the straight line transfer function is exactly represented by the actual transfer function. therefore, the quantization error will be 1/2 lsb in 8- or 10-bit mode. as a consequence, however, the code width of the ?st (0x000) conversion is only 1/2 lsb and the code width of the last (0xff or 0x3ff) is 1.5 lsb.
chapter 10 analog-to-digital converter (s08adc12v1) mc9s08de60 series data sheet, rev. 3 198 freescale semiconductor for 12-bit conversions the code transitions only after the full code width is present, so the quantization error is ? 1 lsb to 0 lsb and the code width of each step is 1 lsb. 10.6.2.5 linearity errors the adc may also exhibit non-linearity of several forms. every effort has been made to reduce these errors but the system should be aware of them because they affect overall accuracy. these errors are: zero-scale error (e zs ) (sometimes called offset) this error is de?ed as the difference between the actual code width of the ?st conversion and the ideal code width (1/2 lsb in 8-bit or 10-bit modes and 1 lsb in 12-bit mode). if the ?st conversion is 0x001, the difference between the actual 0x001 code width and its ideal (1 lsb) is used. full-scale error (e fs ) ?this error is de?ed as the difference between the actual code width of the last conversion and the ideal code width (1.5 lsb in 8-bit or 10-bit modes and 1 lsb in 12-bit mode). if the last conversion is 0x3fe, the difference between the actual 0x3fe code width and its ideal (1 lsb ) is used. differential non-linearity (dnl) this error is de?ed as the worst-case difference between the actual code width and the ideal code width for all conversions. integral non-linearity (inl) this error is de?ed as the highest-value the (absolute value of the) running sum of dnl achieves. more simply, this is the worst-case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage, for all codes. total unadjusted error (tue) this error is de?ed as the difference between the actual transfer function and the ideal straight-line transfer function and includes all forms of error. 10.6.2.6 code jitter, non-monotonicity, and missing codes analog-to-digital converters are susceptible to three special forms of error. these are code jitter, non-monotonicity, and missing codes. code jitter is when, at certain points, a given input voltage converts to one of two values when sampled repeatedly. ideally, when the input voltage is in?itesimally smaller than the transition voltage, the converter yields the lower code (and vice-versa). however, even small amounts of system noise can cause the converter to be indeterminate (between two codes) for a range of input voltages around the transition voltage. this range is normally around 1/2lsb in 8-bit or 10-bit mode, or around 2 lsb in 12-bit mode, and increases with noise. this error may be reduced by repeatedly sampling the input and averaging the result. additionally the techniques discussed in section 10.6.2.3 reduces this error. non-monotonicity is de?ed as when, except for code jitter, the converter converts to a lower code for a higher input voltage. missing codes are those values never converted for any input value. in 8-bit or 10-bit mode, the adc is guaranteed to be monotonic and have no missing codes.
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 199 chapter 11 inter-integrated circuit (s08iicv2) 11.1 introduction the inter-integrated circuit (iic) provides a method of communication between a number of devices. the interface is designed to operate up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pf. all mc9s08de60 series mcus feature the iic, as shown in the following block diagram. note drive strength must be disabled (dse=0) for the iic pins when using the iic module for correct operation.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 200 freescale semiconductor figure 11-1. mc9s08de60/32 block diagram emphasizing the iic block and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 201 11.1.1 features the iic includes these distinctive features: compatible with iic bus standard multi-master operation software programmable for one of 64 different serial clock frequencies software selectable acknowledge bit interrupt driven byte-by-byte data transfer arbitration lost interrupt with automatic mode switching from master to slave calling address identi?ation interrupt start and stop signal generation/detection repeated start signal generation acknowledge bit generation/detection bus busy detection general call recognition 10-bit address extension 11.1.2 modes of operation a brief description of the iic in the various mcu modes is given here. run mode ?this is the basic mode of operation. to conserve power in this mode, disable the module. wait mode ?the module continues to operate while the mcu is in wait mode and can provide a wake-up interrupt. stop mode ?the iic is inactive in stop3 mode for reduced power consumption. the stop instruction does not affect iic register states. stop2 resets the register contents.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 202 freescale semiconductor 11.1.3 block diagram figure 11-2 is a block diagram of the iic. figure 11-2. iic functional block diagram 11.2 external signal description this section describes each user-accessible pin signal. 11.2.1 scl ?serial clock line the bidirectional scl is the serial clock line of the iic system. 11.2.2 sda ?serial data line the bidirectional sda is the serial data line of the iic system. 11.3 register de?ition this section consists of the iic register descriptions in address order. input sync in/out data shift register address compare interrupt clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl sda address
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 203 refer to the direct-page register summary in the memory chapter of this document for the absolute address assignments for all iic registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 11.3.1 iic address register (iica) 11.3.2 iic frequency divider register (iicf) 76543210 r ad7 ad6 ad5 ad4 ad3 ad2 ad1 0 w reset 00000000 = unimplemented or reserved figure 11-3. iic address register (iica) table 11-1. iica field descriptions field description 7? ad[7:1] slave address. the ad[7:1] ?ld contains the slave address to be used by the iic module. this ?ld is used on the 7-bit address scheme and the lower seven bits of the 10-bit address scheme. 76543210 r mult icr w reset 00000000 figure 11-4. iic frequency divider register (iicf)
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 204 freescale semiconductor for example, if the bus speed is 8 mhz, the table below shows the possible hold time values with different icr and mult selections to achieve an iic baud rate of 100kbps. table 11-2. iicf field descriptions field description 7? mult iic multiplier factor . the mult bits de?e the multiplier factor, mul. this factor, along with the scl divider, generates the iic baud rate. the multiplier factor mul as de?ed by the mult bits is provided below. 00 mul = 01 01 mul = 02 10 mul = 04 11 reserved 5? icr iic clock rate . the icr bits are used to prescale the bus clock for bit rate selection. these bits and the mult bits determine the iic baud rate, the sda hold time, the scl start hold time, and the scl stop hold time. table 11-4 provides the scl divider and hold values for corresponding values of the icr. the scl divider multiplied by multiplier factor mul generates iic baud rate. eqn. 11-1 sda hold time is the delay from the falling edge of scl (iic clock) to the changing of sda (iic data). sda hold time = bus period (s) mul sda hold value eqn. 11-2 scl start hold time is the delay from the falling edge of sda (iic data) while scl is high (start condition) to the falling edge of scl (iic clock). scl start hold time = bus period (s) mul scl start hold value eqn. 11-3 scl stop hold time is the delay from the rising edge of scl (iic clock) to the rising edge of sda sda (iic data) while scl is high (stop condition). scl stop hold time = bus period (s) mul scl stop hold value eqn. 11-4 table 11-3. hold time values for 8 mhz bus speed mult icr hold times ( s) sda scl start scl stop 0x2 0x00 3.500 3.000 5.500 0x1 0x07 2.500 4.000 5.250 0x1 0x0b 2.250 4.000 5.250 0x0 0x14 2.125 4.250 5.125 0x0 0x18 1.125 4.750 5.125 iic baud rate bus speed (hz) mul scldivider -------------------------------------------- - =
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 205 table 11-4. iic divider and hold values icr (hex) scl divider sda hold value scl hold (start) value sda hold (stop) value icr (hex) scl divider sda hold value scl hold (start) value scl hold (stop) value 00 20 7 6 11 20 160 17 78 81 01 22 7 7 12 21 192 17 94 97 02 24 8 8 13 22 224 33 110 113 03 26 8 9 14 23 256 33 126 129 04 28 9 10 15 24 288 49 142 145 05 30 9 11 16 25 320 49 158 161 06 34 10 13 18 26 384 65 190 193 07 40 10 16 21 27 480 65 238 241 08 28 7 10 15 28 320 33 158 161 09 32 7 12 17 29 384 33 190 193 0a 36 9 14 19 2a 448 65 222 225 0b 40 9 16 21 2b 512 65 254 257 0c 44 11 18 23 2c 576 97 286 289 0d 48 11 20 25 2d 640 97 318 321 0e 56 13 24 29 2e 768 129 382 385 0f 68 13 30 35 2f 960 129 478 481 10 48 9 18 25 30 640 65 318 321 11 56 9 22 29 31 768 65 382 385 12 64 13 26 33 32 896 129 446 449 13 72 13 30 37 33 1024 129 510 513 14 80 17 34 41 34 1152 193 574 577 15 88 17 38 45 35 1280 193 638 641 16 104 21 46 53 36 1536 257 766 769 17 128 21 58 65 37 1920 257 958 961 18 80 9 38 41 38 1280 129 638 641 19 96 9 46 49 39 1536 129 766 769 1a 112 17 54 57 3a 1792 257 894 897 1b 128 17 62 65 3b 2048 257 1022 1025 1c 144 25 70 73 3c 2304 385 1150 1153 1d 160 25 78 81 3d 2560 385 1278 1281 1e 192 33 94 97 3e 3072 513 1534 1537 1f 240 33 118 121 3f 3840 513 1918 1921
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 206 freescale semiconductor 11.3.3 iic control register (iicc1) 76543210 r iicen iicie mst tx txak 000 w rsta reset 00000000 = unimplemented or reserved figure 11-5. iic control register (iicc1) table 11-5. iicc1 field descriptions field description 7 iicen iic enable. the iicen bit determines whether the iic module is enabled. 0 iic is not enabled 1 iic is enabled 6 iicie iic interrupt enable. the iicie bit determines whether an iic interrupt is requested. 0 iic interrupt request not enabled 1 iic interrupt request enabled 5 mst master mode select. the mst bit changes from a 0 to a 1 when a start signal is generated on the bus and master mode is selected. when this bit changes from a 1 to a 0 a stop signal is generated and the mode of operation changes from master to slave. 0 slave mode 1 master mode 4 tx transmit mode select. the tx bit selects the direction of master and slave transfers. in master mode, this bit should be set according to the type of transfer required. therefore, for address cycles, this bit is always high. when addressed as a slave, this bit should be set by software according to the srw bit in the status register. 0 receive 1 transmit 3 txak transmit acknowledge enable. this bit speci?s the value driven onto the sda during data acknowledge cycles for master and slave receivers. 0 an acknowledge signal is sent out to the bus after receiving one data byte 1 no acknowledge signal response is sent 2 rsta repeat start. writing a 1 to this bit generates a repeated start condition provided it is the current master. this bit is always read as cleared. attempting a repeat at the wrong time results in loss of arbitration.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 207 11.3.4 iic status register (iics) 76543210 r tcf iaas busy arbl 0srw iicif rxak w reset 10000000 = unimplemented or reserved figure 11-6. iic status register (iics) table 11-6. iics field descriptions field description 7 tcf transfer complete flag. this bit is set on the completion of a byte transfer. this bit is only valid during or immediately following a transfer to the iic module or from the iic module.the tcf bit is cleared by reading the iicd register in receive mode or writing to the iicd in transmit mode. 0 transfer in progress 1 transfer complete 6 iaas addressed as a slave. the iaas bit is set when the calling address matches the programmed slave address or when the gcaen bit is set and a general call is received. writing the iicc register clears this bit. 0 not addressed 1 addressed as a slave 5 busy bus busy. the busy bit indicates the status of the bus regardless of slave or master mode. the busy bit is set when a start signal is detected and cleared when a stop signal is detected. 0 bus is idle 1 bus is busy 4 arbl arbitration lost. this bit is set by hardware when the arbitration procedure is lost. the arbl bit must be cleared by software by writing a 1 to it. 0 standard bus operation 1 loss of arbitration 2 srw slave read/write. when addressed as a slave, the srw bit indicates the value of the r/w command bit of the calling address sent to the master. 0 slave receive, master writing to slave 1 slave transmit, master reading from slave 1 iicif iic interrupt flag. the iicif bit is set when an interrupt is pending. this bit must be cleared by software, by writing a 1 to it in the interrupt routine. one of the following events can set the iicif bit: one byte transfer completes match of slave address to calling address arbitration lost 0 no interrupt pending 1 interrupt pending 0 rxak receive acknowledge . when the rxak bit is low, it indicates an acknowledge signal has been received after the completion of one byte of data transmission on the bus. if the rxak bit is high it means that no acknowledge signal is detected. 0 acknowledge received 1 no acknowledge received
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 208 freescale semiconductor 11.3.5 iic data i/o register (iicd) note when transitioning out of master receive mode, the iic mode should be switched before reading the iicd register to prevent an inadvertent initiation of a master receive data transfer. in slave mode, the same functions are available after an address match has occurred. the tx bit in iicc must correctly re?ct the desired direction of transfer in master and slave modes for the transmission to begin. for instance, if the iic is con?ured for master transmit but a master receive is desired, reading the iicd does not initiate the receive. reading the iicd returns the last byte received while the iic is con?ured in master receive or slave receive modes. the iicd does not re?ct every byte transmitted on the iic bus, nor can software verify that a byte has been written to the iicd correctly by reading it back. in master transmit mode, the ?st byte of data written to iicd following assertion of mst is used for the address transfer and should comprise of the calling address (in bit 7 to bit 1) concatenated with the required r/ w bit (in position bit 0). 11.3.6 iic control register 2 (iicc2) 76543210 r data w reset 00000000 figure 11-7. iic data i/o register (iicd) table 11-7. iicd field descriptions field description 7? data data in master transmit mode, when data is written to the iicd, a data transfer is initiated. the most signi?ant bit is sent ?st. in master receive mode, reading this register initiates receiving of the next byte of data. 76543210 r gcaen adext 000 ad10 ad9 ad8 w reset 00000000 = unimplemented or reserved figure 11-8. iic control register (iicc2)
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 209 11.4 functional description this section provides a complete functional description of the iic module. 11.4.1 iic protocol the iic bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logic and function is exercised on both lines with external pull-up resistors. the value of these resistors is system dependent. normally, a standard communication is composed of four parts: start signal slave address transmission data transfer stop signal the stop signal should not be confused with the cpu stop instruction. the iic bus system communication is described brie? in the following sections and illustrated in figure 11-9 . table 11-8. iicc2 field descriptions field description 7 gcaen general call address enable. the gcaen bit enables or disables general call address. 0 general call address is disabled 1 general call address is enabled 6 adext address extension. the adext bit controls the number of bits used for the slave address. 0 7-bit address scheme 1 10-bit address scheme 2? ad[10:8] slave address. the ad[10:8] ?ld contains the upper three bits of the slave address in the 10-bit address scheme. this ?ld is only valid when the adext bit is set.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 210 freescale semiconductor figure 11-9. iic bus transmission signals 11.4.1.1 start signal when the bus is free, no master device is engaging the bus (scl and sda lines are at logical high), a master may initiate communication by sending a start signal. as shown in figure 11-9 , a start signal is de?ed as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle states. 11.4.1.2 slave address transmission the ?st byte of data transferred immediately after the start signal is the slave address transmitted by the master. this is a seven-bit calling address followed by a r/ w bit. the r/ w bit tells the slave the desired direction of data transfer. 1 = read transfer, the slave transmits data to the master. 0 = write transfer, the master transmits data to the slave. only the slave with a calling address that matches the one transmitted by the master responds by sending back an acknowledge bit. this is done by pulling the sda low at the ninth clock (see figure 11-9 ). no two slaves in the system may have the same address. if the iic module is the master, it must not transmit an address equal to its own slave address. the iic cannot be master and slave at the same time. however, if arbitration is lost during an address cycle, the iic reverts to slave mode and operates correctly even if it is being addressed by another master. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 12 5 678 msb lsb repeated 34 99 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit wr ite start signal start signal ack bit calling address read/ wr ite stop signal no ack bit read/ wr ite
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 211 11.4.1.3 data transfer before successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction speci?d by the r/ w bit sent by the calling master. all transfers that come after an address cycle are referred to as data transfers, even if they carry sub-address information for the slave device each data byte is 8 bits long. data may be changed only while scl is low and must be held stable while scl is high as shown in figure 11-9 . there is one clock pulse on scl for each data bit, the msb being transferred ?st. each data byte is followed by a 9th (acknowledge) bit, which is signalled from the receiving device. an acknowledge is signalled by pulling the sda low at the ninth clock. in summary, one complete data transfer needs nine clock pulses. if the slave receiver does not acknowledge the master in the ninth bit time, the sda line must be left high by the slave. the master interprets the failed acknowledge as an unsuccessful data transfer. if the master receiver does not acknowledge the slave transmitter after a data byte transmission, the slave interprets this as an end of data transfer and releases the sda line. in either case, the data transfer is aborted and the master does one of two things: relinquishes the bus by generating a stop signal. commences a new calling by generating a repeated start signal. 11.4.1.4 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal ?st. this is called repeated start. a stop signal is de?ed as a low-to-high transition of sda while scl at logical 1 (see figure 11-9 ). the master can generate a stop even if the slave has generated an acknowledge at which point the slave must release the bus. 11.4.1.5 repeated start signal as shown in figure 11-9 , a repeated start signal is a start signal generated without ?st generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 11.4.1.6 arbitration procedure the iic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure, a bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. the losing masters immediately switch over to slave receive mode and stop driving sda output. in this case,
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 212 freescale semiconductor the transition from master to slave mode does not generate a stop condition. meanwhile, a status bit is set by hardware to indicate loss of arbitration. 11.4.1.7 clock synchronization because wire-and logic is performed on the scl line, a high-to-low transition on the scl line affects all the devices connected on the bus. the devices start counting their low period and after a devices clock has gone low, it holds the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. therefore, synchronized clock scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 11-10 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the device clocks and the state of the scl line and all the devices start counting their high periods. the ?st device to complete its high period pulls the scl line low again. figure 11-10. iic clock synchronization 11.4.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte transfer (9 bits). in such a case, it halts the bus clock and forces the master clock into wait states until the slave releases the scl line. 11.4.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. scl1 scl2 scl internal counter reset delay start counting high period
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 213 11.4.2 10-bit address for 10-bit addressing, 0x11110 is used for the ?st 5 bits of the ?st address byte. various combinations of read/write formats are possible within a transfer that includes 10-bit addressing. 11.4.2.1 master-transmitter addresses a slave-receiver the transfer direction is not changed (see table 11-9 ). when a 10-bit address follows a start condition, each slave compares the first seven bits of the first byte of the slave address (11110xx) with its own address and tests whether the eighth bit (r/ w direction bit) is 0. more than one device can find a match and generate an acknowledge (a1). then, each slave that finds a match compares the eight bits of the second byte of the slave address with its own address. only one slave finds a match and generates an acknowledge (a2). the matching slave remains addressed by the master until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. 11.4.2.2 master-receiver addresses a slave-transmitter the transfer direction is changed after the second r/ w bit (see table 11-10 ). up to and including acknowledge bit a2, the procedure is the same as that described for a master-transmitter addressing a slave-receiver. after the repeated start condition (sr), a matching slave remembers that it was addressed before. this slave then checks whether the ?st seven bits of the ?st byte of the slave address following sr are the same as they were after the start condition (s) and tests whether the eighth (r/ w) bit is 1. if there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge a3. the slave-transmitter remains addressed until it receives a stop condition (p) or a repeated start condition (sr) followed by a different slave address. after a repeated start condition (sr), all other slave devices also compare the ?st seven bits of the ?st byte of the slave address with their own addresses and test the eighth (r/ w) bit. however, none of them are addressed because r/ w = 1 (for 10-bit devices) or the 11110xx slave address (for 7-bit devices) does not match. after the master-receiver has sent the ?st byte of the 10-bit address, the slave-transmitter sees an iic interrupt. software must ensure the contents of iicd are ignored and not treated as valid data for this interrupt. s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 data a ... data a/a p 11110 + ad10 + ad9 0 ad[8:1] table 11-9. master-transmitter addresses slave-receiver with a 10-bit address s slave address 1st 7 bits r/w a1 slave address 2nd byte a2 sr slave address 1st 7 bits r/w a3 data a ... data a p 11110 + ad10 + ad9 0 ad[8:1] 11110 + ad10 + ad9 1 table 11-10. master-receiver addresses a slave-transmitter with a 10-bit address
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 214 freescale semiconductor 11.4.3 general call address general calls can be requested in 7-bit address or 10-bit address. if the gcaen bit is set, the iic matches the general call address as well as its own slave address. when the iic responds to a general call, it acts as a slave-receiver and the iaas bit is set after the address cycle. software must read the iicd register after the ?st byte transfer to determine whether the address matches is its own slave address or a general call. if the value is 00, the match is a general call. if the gcaen bit is clear, the iic ignores any data supplied from a general call address by not issuing an acknowledgement. 11.5 resets the iic is disabled after reset. the iic cannot cause an mcu reset. 11.6 interrupts the iic generates a single interrupt. an interrupt from the iic is generated when any of the events in table 11-11 occur, provided the iicie bit is set. the interrupt is driven by bit iicif (of the iic status register) and masked with bit iicie (of the iic control register). the iicif bit must be cleared by software by writing a 1 to it in the interrupt routine. you can determine the interrupt type by reading the status register. 11.6.1 byte transfer interrupt the tcf (transfer complete ?g) bit is set at the falling edge of the ninth clock to indicate the completion of byte transfer. 11.6.2 address detect interrupt when the calling address matches the programmed slave address (iic address register) or when the gcaen bit is set and a general call is received, the iaas bit in the status register is set. the cpu is interrupted, provided the iicie is set. the cpu must check the srw bit and set its tx mode accordingly. 11.6.3 arbitration lost interrupt the iic is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, the relative priority of the contending masters is determined by a data arbitration procedure. the iic module asserts this interrupt when it loses the data arbitration process and the arbl bit in the status register is set. table 11-11. interrupt summary interrupt source status flag local enable complete 1-byte transfer tcf iicif iicie match of received calling address iaas iicif iicie arbitration lost arbl iicif iicie
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 215 arbitration is lost in the following circumstances: sda sampled as a low when the master drives a high during an address or data transmit cycle. sda sampled as a low when the master drives a high during the acknowledge bit of a data receive cycle. a start cycle is attempted when the bus is busy. a repeated start cycle is requested in slave mode. a stop condition is detected when the master did not request it. this bit must be cleared by software writing a 1 to it.
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 216 freescale semiconductor 11.7 initialization/application information figure 11-11. iic module quick start module initialization (slave) 1. write: iicc2 to enable or disable general call to select 10-bit or 7-bit addressing mode 2. write: iica to set the slave address 3. write: iicc1 to enable iic and interrupts 4. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 5. initialize ram variables used to achieve the routine shown in figure 11-12 module initialization (master) 1. write: iicf to set the iic baud rate (example provided in this chapter) 2. write: iicc1 to enable iic and interrupts 3. initialize ram variables (iicen = 1 and iicie = 1) for transmit data 4. initialize ram variables used to achieve the routine shown in figure 11-12 5. write: iicc1 to enable tx 6. write: iicc1 to enable mst (master mode) 7. write: iicd with the address of the target slave. (the lsb of this byte determines whether the communication is master receive or transmit.) module use the routine shown in figure 11-12 can handle both master and slave iic operations. for slave operation, an incoming iic message that contains the proper address begins iic communication. for master operation, communication must be initiated by writing to the iicd register. 0 iicf iica baud rate = busclk / (2 x mult x (scl divider)) tx txak rsta 0 0 iicc1 iicen iicie mst module con?uration arbl 0 srw iicif rxak iics tcf iaas busy module status ?gs register model ad[7:1] when addressed as a slave (in slave mode), the module responds to this address mult icr iicd data data register; write to transmit iic data read to read iic data 0 ad10 ad9 ad8 iicc2 gcaen adext address con?uration 0 0
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 217 figure 11-12. typical iic interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to iicd switch to rx mode dummy read from iicd generate stop signal read data from iicd and store set txack =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear arbl iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to iicd set rx mode dummy read from iicd ack from receiver ? tx next byte read data from iicd and store switch to rx mode dummy read from iicd rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iicif address transfer data transfer (mst = 0) (mst = 0) see note 1 notes: 1. if general call is enabled, a check must be done to determine whether the received address was a general call address (0x00). if the received address was a general call address, then the general call must be handled by user software. 2. when 10-bit addressing is used to address a slave, the slave sees an interrupt following the ?st byte of the extended address. user software must ensure that for this interrupt, the contents of iicd are ignored and not treated as a valid data transfer see note 2
chapter 11 inter-integrated circuit (s08iicv2) mc9s08de60 series data sheet, rev. 3 218 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 219 chapter 12 freescale controller area network (s08mscanv1) 12.1 introduction the freescale controller area network (mscan) is a communication controller implementing the can 2.0a/b protocol as de?ed in the bosch speci?ation dated september 1991. to fully understand the mscan speci?ation, it is recommended that the bosch speci?ation be read ?st to gain familiarity with the terms and concepts contained within this document. though not exclusively intended for automotive applications, can protocol is designed to meet the speci? requirements of a vehicle serial data bus: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, and required bandwidth. mscan uses an advanced buffer arrangement resulting in predictable real-time behavior and simpli?d application software. the mscan module is available in all devices in the mc9s08de60 series.
chapter 12 freescale controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 220 freescale semiconductor figure 12-1. mc9s08de60/32 block diagram emphasizing the mscan block and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 221 12.1.1 features the basic features of the mscan are as follows: implementation of the can protocol ?version 2.0a/b standard and extended data frames zero to eight bytes data length programmable bit rate up to 1 mbps 1 support for remote frames five receive buffers with fifo storage scheme three transmit buffers with internal prioritization using a ?ocal priority?concept flexible maskable identi?r ?ter supports two full-size (32-bit) extended identi?r ?ters, or four 16-bit ?ters, or eight 8-bit ?ters programmable wakeup functionality with integrated low-pass ?ter programmable loopback mode supports self-test operation programmable listen-only mode for monitoring of can bus programmable bus-off recovery functionality separate signalling and interrupt capabilities for all can receiver and transmitter error states (warning, error passive, bus-off) programmable mscan clock source either bus clock or oscillator clock internal timer for time-stamping of received and transmitted messages three low-power modes: sleep, power down, and mscan enable global initialization of con?uration registers 12.1.2 modes of operation the following modes of operation are speci? to the mscan. see section 12.5, ?unctional description , for details. listen-only mode mscan sleep mode mscan initialization mode mscan power down mode loopback self test mode 1. depending on the actual bit timing and the clock jitter of the pll.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 222 freescale semiconductor 12.1.3 block diagram figure 12-2. mscan block diagram 12.2 external signal description the mscan uses two external pins: 12.2.1 rxcan ?can receiver input pin rxcan is the mscan receiver input pin. 12.2.2 txcan ?can transmitter output pin txcan is the mscan transmitter output pin. the txcan output pin represents the logic level on the can bus: 0 = dominant state 1 = recessive state 12.2.3 can system a typical can system with mscan is shown in figure 12-3 . each can node is connected physically to the can bus lines through a transceiver device. the transceiver is capable of driving the large current needed for the can bus and has current protection against defective can or defective nodes. rxcan txcan receive/ transmit engine message filtering and buffering control and status wake-up interrupt req. errors interrupt req. receive interrupt req. transmit interrupt req. canclk bus clock con?uration oscillator clock mux presc. tq clk mscan low pass filter wake-up registers
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 223 figure 12-3. can system 12.3 register de?ition this section describes in detail all the registers and register bits in the mscan module. each description includes a standard register diagram with an associated ?ure number. details of register bit and ?ld function follow the register diagrams, in bit order. all bits of all registers in this module are completely synchronous to internal clocks during a register read. 12.3.1 mscan control register 0 (canctl0) the canctl0 register provides various control bits of the mscan module as described below. note the canctl0 register, except wupe, initrq, and slprq, is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). read: anytime write: anytime when out of initialization mode; exceptions are read-only rxact and synch, rxfrm (which is set by the module only), and initrq (which is also writable in initialization mode). 76543210 r rxfrm rxact cswai synch time wupe slprq initrq w reset: 00000001 = unimplemented figure 12-4. mscan control register 0 (canctl0) can bus can controller (mscan) transceiver can node 1 can node 2 can node n can_l can_h mcu txcan rxcan
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 224 freescale semiconductor table 12-1. canctl0 register field descriptions field description 7 rxfrm 1 received frame flag this bit is read and clear only. it is set when a receiver has received a valid message correctly, independently of the ?ter con?uration. after it is set, it remains set until cleared by software or reset. clearing is done by writing a 1. writing a 0 is ignored. this bit is not valid in loopback mode. 0 no valid message was received since last clearing this ?g 1 a valid message was received since last clearing of this ?g 6 rxact receiver active status ?this read-only ?g indicates the mscan is receiving a message. the ?g is controlled by the receiver front end. this bit is not valid in loopback mode. 0 mscan is transmitting or idle 2 1 mscan is receiving a message (including when arbitration is lost) 2 5 cswai 3 can stops in wait mode enabling this bit allows for lower power consumption in wait mode by disabling all the clocks at the cpu bus interface to the mscan module. 0 the module is not affected during wait mode 1 the module ceases to be clocked during wait mode 4 synch synchronized status this read-only ?g indicates whether the mscan is synchronized to the can bus and able to participate in the communication process. it is set and cleared by the mscan. 0 mscan is not synchronized to the can bus 1 mscan is synchronized to the can bus 3 time timer enable this bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate. if the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the active tx/rx buffer. as soon as a message is acknowledged on the can bus, the time stamp will be written to the highest bytes (0x000e, 0x000f) in the appropriate buffer (see section 12.4, ?rogrammers model of message storage ?. the internal timer is reset (all bits set to 0) when disabled. this bit is held low in initialization mode. 0 disable internal mscan timer 1 enable internal mscan timer 2 wupe 4 wake-up enable this con?uration bit allows the mscan to restart from sleep mode when traf? on can is detected (see section 12.5.5.4, ?scan sleep mode ?. this bit must be con?ured before sleep mode entry for the selected function to take effect. 0 wake-up disabled ?the mscan ignores traf? on can 1 wake-up enabled ?the mscan is able to restart
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 225 1 slprq 5 sleep mode request ?this bit requests the mscan to enter sleep mode, which is an internal power saving mode (see section 12.5.5.4, ?scan sleep mode ?. the sleep mode request is serviced when the can bus is idle, i.e., the module is not receiving a message and all transmit buffers are empty. the module indicates entry to sleep mode by setting slpak = 1 (see section 12.3.2, ?scan control register 1 (canctl1) ?. slprq cannot be set while the wupif ?g is set (see section 12.3.4.1, ?scan receiver flag register (canrflg) ?. sleep mode will be active until slprq is cleared by the cpu or, depending on the setting of wupe, the mscan detects activity on the can bus and clears slprq itself. 0 running ?the mscan functions normally 1 sleep mode request ?the mscan enters sleep mode when can bus idle 0 initrq 6,7 initialization mode request ?when this bit is set by the cpu, the mscan skips to initialization mode (see section 12.5.5.5, ?scan initialization mode ?. any ongoing transmission or reception is aborted and synchronization to the can bus is lost. the module indicates entry to initialization mode by setting initak = 1 ( section 12.3.2, ?scan control register 1 (canctl1) ?. the following registers enter their hard reset state and restore their default values: canctl0 8 , canrflg 9 , canrier 10 , cantflg, cantier, cantarq, cantaak, and cantbsel. the registers canctl1, canbtr0, canbtr1, canidac, canidar0-7, and canidmr0-7 can only be written by the cpu when the mscan is in initialization mode (initrq = 1 and initak = 1). the values of the error counters are not affected by initialization mode. when this bit is cleared by the cpu, the mscan restarts and then tries to synchronize to the can bus. if the mscan is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the can bus; if the mscan is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits. writing to other bits in canctl0, canrflg, canrier, cantflg, or cantier must be done only after initialization mode is exited, which is initrq = 0 and initak = 0. 0 normal operation 1 mscan in initialization mode 1 the mscan must be in normal mode for this bit to become set. 2 see the bosch can 2.0a/b speci?ation for a detailed de?ition of transmitter and receiver states. 3 in order to protect from accidentally violating the can protocol, the txcan pin is immediately forced to a recessive state when the cpu enters wait (cswai = 1) or stop mode (see section 12.5.5.2, ?peration in wait mode ?and section 12.5.5.3, ?peration in stop mode ? . 4 the cpu has to make sure that the wupe bit and the wupie wake-up interrupt enable bit (see section 12.3.5, ?scan receiver interrupt enable register (canrier) ) is enabled, if the recovery mechanism from stop or wait is required. 5 the cpu cannot clear slprq before the mscan has entered sleep mode (slprq = 1 and slpak = 1). 6 the cpu cannot clear initrq before the mscan has entered initialization mode (initrq = 1 and initak = 1). 7 in order to protect from accidentally violating the can protocol, the txcan pin is immediately forced to a recessive state when the initialization mode is requested by the cpu. thus, the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before requesting initialization mode. 8 not including wupe, initrq, and slprq. 9 tstat1 and tstat0 are not affected by initialization mode. 10 rstat1 and rstat0 are not affected by initialization mode. table 12-1. canctl0 register field descriptions (continued) field description
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 226 freescale semiconductor 12.3.2 mscan control register 1 (canctl1) the canctl1 register provides various control bits and handshake status information of the mscan module as described below. figure 12-5. mscan control register 1(canctl1) read: anytime write: anytime when initrq = 1 and initak = 1, except cane which is write once in normal and anytime in special system operation modes when the mscan is in initialization mode (initrq = 1 and initak = 1). 76543210 r cane clksrc loopb listen borm wupm slpak initak w reset: 00010001 = unimplemented table 12-2. canctl1 register field descriptions field description 7 cane mscan enable 0 mscan module is disabled 1 mscan module is enabled 6 clksrc mscan clock source this bit de?es the clock source for the mscan module (only for systems with a clock generation module; section 12.5.3.3, ?lock system , and section figure 12-42., ?scan clocking scheme ,?. 0 mscan clock source is the oscillator clock 1 mscan clock source is the bus clock 5 loopb loopback self test mode when this bit is set, the mscan performs an internal loopback which can be used for self test operation. the bit stream output of the transmitter is fed back to the receiver internally. section 12.5.4.6, ?oopback self test mode . 0 loopback self test disabled 1 loopback self test enabled 4 listen listen only mode this bit con?ures the mscan as a can bus monitor. when listen is set, all valid can messages with matching id are received, but no acknowledgement or error frames are sent out (see section 12.5.4.4, ?isten-only mode ?. in addition, the error counters are frozen. listen only mode supports applications which require ?ot plugging?or throughput analysis. the mscan is unable to transmit any messages when listen only mode is active. 0 normal operation 1 listen only mode activated 3 borm bus-off recovery mode ?this bits con?ures the bus-off state recovery mode of the mscan. refer to section 12.6.2, ?us-off recovery ,?for details. 0 automatic bus-off recovery (see bosch can 2.0a/b protocol speci?ation) 1 bus-off recovery upon user request 2 wupm wake-up mode ?if wupe in canctl0 is enabled, this bit de?es whether the integrated low-pass ?ter is applied to protect the mscan from spurious wake-up (see section 12.5.5.4, ?scan sleep mode ?. 0 mscan wakes up on any dominant level on the can bus 1 mscan wakes up only in case of a dominant pulse on the can bus that has a length of t wup
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 227 12.3.3 mscan bus timing register 0 (canbtr0) the canbtr0 register con?ures various can bus timing parameters of the mscan module. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 1 slpak sleep mode acknowledge ?this ?g indicates whether the mscan module has entered sleep mode (see section 12.5.5.4, ?scan sleep mode ?. it is used as a handshake ?g for the slprq sleep mode request. sleep mode is active when slprq = 1 and slpak = 1. depending on the setting of wupe, the mscan will clear the ?g if it detects activity on the can bus while in sleep mode.cpu clearing the slprq bit will also reset the slpak bit. 0 running ?the mscan operates normally 1 sleep mode active ?the mscan has entered sleep mode 0 initak initialization mode acknowledge ?this ?g indicates whether the mscan module is in initialization mode (see section 12.5.5.5, ?scan initialization mode ?. it is used as a handshake ?g for the initrq initialization mode request. initialization mode is active when initrq = 1 and initak = 1. the registers canctl1, canbtr0, canbtr1, canidac, canidar0?anidar7, and canidmr0?anidmr7 can be written only by the cpu when the mscan is in initialization mode. 0 running ?the mscan operates normally 1 initialization mode active ?the mscan is in initialization mode 76543210 r sjw1 sjw0 brp5 brp4 brp3 brp2 brp1 brp0 w reset: 00000000 figure 12-6. mscan bus timing register 0 (canbtr 0) table 12-3. canbtr 0 register field descriptions field description 7:6 sjw[1:0] synchronization jump width the synchronization jump width de?es the maximum number of time quanta (tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the can bus (see table 12-4 ). 5:0 brp[5:0] baud rate prescaler these bits determine the time quanta (tq) clock which is used to build up the bit timing (see table 12-5 ). table 12-4. synchronization jump width sjw1 sjw0 synchronization jump width 0 0 1 tq clock cycle 0 1 2 tq clock cycles 1 0 3 tq clock cycles 1 1 4 tq clock cycles table 12-2. canctl1 register field descriptions (continued) field description
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 228 freescale semiconductor 12.3.4 mscan bus timing register 1 (canbtr1) the canbtr1 register con?ures various can bus timing parameters of the mscan module. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) table 12-5. baud rate prescaler brp5 brp4 brp3 brp2 brp1 brp0 prescaler value (p) 000000 1 000001 2 000010 3 000011 4 :::::: : 111111 64 76543210 r samp tseg22 tseg21 tseg20 tseg13 tseg12 tseg11 tseg10 w reset: 00000000 figure 12-7. mscan bus timing register 1 (canbtr1) table 12-6. canbtr1 register field descriptions field description 7 samp sampling ?this bit determines the number of can bus samples taken per bit time. 0 one sample per bit. 1 three samples per bit 1 . if samp = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. if samp = 1, the resulting bit value is determined by using majority rule on the three total samples. for higher bit rates, it is recommended that only one sample is taken per bit time (samp = 0). 1 in this case, phase_seg1 must be at least 2 time quanta (tq). 6:4 tseg2[2:0] time segment 2 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 12-43 ). time segment 2 (tseg2) values are programmable as shown in table 12-7 . 3:0 tseg1[3:0] time segment 1 time segments within the bit time ? the number of clock cycles per bit time and the location of the sample point (see figure 12-43 ). time segment 1 (tseg1) values are programmable as shown in table 12-8 .
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 229 the bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (tq) clock cycles per bit (as shown in table 12-7 and table 12-8 ). eqn. 12-1 12.3.4.1 mscan receiver flag register (canrflg) a ?g can be cleared only by software (writing a 1 to the corresponding bit position) when the condition which caused the setting is no longer valid. every ?g has an associated interrupt enable bit in the canrier register. table 12-7. time segment 2 values tseg22 tseg21 tseg20 time segment 2 0 0 0 1 tq clock cycle 1 1 this setting is not valid. please refer to table 12-35 for valid settings. 0 0 1 2 tq clock cycles ::: : 1 1 0 7 tq clock cycles 1 1 1 8 tq clock cycles table 12-8. time segment 1 values tseg13 tseg12 tseg11 tseg10 time segment 1 0 0 0 0 1 tq clock cycle 1 1 this setting is not valid. please refer to table 12-35 for valid settings. 0 0 0 1 2 tq clock cycles 1 0 0 1 0 3 tq clock cycles 1 0 0 1 1 4 tq clock cycles :::: : 1 1 1 0 15 tq clock cycles 1 1 1 1 16 tq clock cycles 76543210 r wupif cscif rstat1 rstat0 tstat1 tstat0 ovrif rxf w reset: 00000000 = unimplemented figure 12-8. mscan receiver flag register (canrflg) bit time prescaler value () f canclk ----------------------------------------------------- - 1 timesegment1 timesegment2 ++ () ? =
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 230 freescale semiconductor note the canrflg register is held in the reset state 1 when the initialization mode is active (initrq = 1 and initak = 1). this register is writable again as soon as the initialization mode is exited (initrq = 0 and initak = 0). read: anytime write: anytime when out of initialization mode, except rstat[1:0] and tstat[1:0] ?gs which are read-only; write of 1 clears ?g; write of 0 is ignored. 1. the rstat[1:0], tstat[1:0] bits are not affected by initialization mode. table 12-9. canrflg register field descriptions field description 7 wupif wake-up interrupt flag ?if the mscan detects can bus activity while in sleep mode (see section 12.5.5.4, ?scan sleep mode ,? and wupe = 1 in cantctl0 (see section 12.3.1, ?scan control register 0 (canctl0) ?, the module will set wupif. if not masked, a wake-up interrupt is pending while this ?g is set. 0 no wake-up activity observed while in sleep mode 1 mscan detected activity on the can bus and requested wake-up 6 cscif can status change interrupt flag ?this ?g is set when the mscan changes its current can bus status due to the actual value of the transmit error counter (tec) and the receive error counter (rec). an additional 4-bit (rstat[1:0], tstat[1:0]) status register, which is split into separate sections for tec/rec, informs the system on the actual can bus status (see section 12.3.5, ?scan receiver interrupt enable register (canrier) ?. if not masked, an error interrupt is pending while this ?g is set. cscif provides a blocking interrupt. that guarantees that the receiver/transmitter status bits (rstat/tstat) are only updated when no can status change interrupt is pending. if the tecs/recs change their current value after the cscif is asserted, which would cause an additional state change in the rstat/tstat bits, these bits keep their status until the current cscif interrupt is cleared again. 0 no change in can bus status occurred since last interrupt 1 mscan changed current can bus status 5:4 rstat[1:0] receiver status bits ?the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate receiver related can bus status of the mscan. the coding for the bits rstat1, rstat0 is: 00 rxok: 0 receive error counter 96 01 rxwrn: 96 < receive error counter 127 10 rxerr: 127 < receive error counter 11 bus-off 1 : transmit error counter > 255 3:2 tstat[1:0] transmitter status bits ?the values of the error counters control the actual can bus status of the mscan. as soon as the status change interrupt ?g (cscif) is set, these bits indicate the appropriate transmitter related can bus status of the mscan. the coding for the bits tstat1, tstat0 is: 00 txok: 0 transmit error counter 96 01 txwrn: 96 < transmit error counter 127 10 txerr: 127 < transmit error counter 255 11 bus-off: transmit error counter > 255
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 231 12.3.5 mscan receiver interrupt enable register (canrier) this register contains the interrupt enable bits for the interrupt ?gs described in the canrflg register. note the canrier register is held in the reset state when the initialization mode is active (initrq=1 and initak=1). this register is writable when not in initialization mode (initrq=0 and initak=0). the rstate[1:0], tstate[1:0] bits are not affected by initialization mode. read: anytime write: anytime when not in initialization mode 1 ovrif overrun interrupt flag this ?g is set when a data overrun condition occurs. if not masked, an error interrupt is pending while this ?g is set. 0 no data overrun condition 1 a data overrun detected 0 rxf 2 receive buffer full flag rxf is set by the mscan when a new message is shifted in the receiver fifo. this ?g indicates whether the shifted buffer is loaded with a correctly received message (matching identi?r, matching cyclic redundancy code (crc) and no other errors detected). after the cpu has read that message from the rxfg buffer in the receiver fifo, the rxf ?g must be cleared to release the buffer. a set rxf ?g prohibits the shifting of the next fifo entry into the foreground buffer (rxfg). if not masked, a receive interrupt is pending while this ?g is set. 0 no new message available within the rxfg 1 the receiver fifo is not empty. a new message is available in the rxfg 1 redundant information for the most critical can bus status which is ?us-off? this only occurs if the tx error counter exceeds a number of 255 errors. bus-off affects the receiver state. as soon as the transmitter leaves its bus-off state the receiver state skips to rxok too. refer also to tstat[1:0] coding in this register. 2 to ensure data integrity, do not read the receive buffer registers while the rxf ?g is cleared. for mcus with dual cpus, reading the receive buffer registers while the rxf ?g is cleared may result in a cpu fault condition. 76543210 r wupie cscie rstate1 rstate0 tstate1 tstate0 ovrie rxfie w reset: 00000000 figure 12-9. mscan receiver interrupt enable register (canrier) table 12-9. canrflg register field descriptions (continued) field description
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 232 freescale semiconductor 12.3.6 mscan transmitter flag register (cantflg) the transmit buffer empty ?gs each have an associated interrupt enable bit in the cantier register. table 12-10. canrier register field descriptions field description 7 wupie 1 1 wupie and wupe (see section 12.3.1, ?scan control register 0 (canctl0) ? must both be enabled if the recovery mechanism from stop or wait is required. wake-up interrupt enable 0 no interrupt request is generated from this event. 1 a wake-up event causes a wake-up interrupt request. 6 cscie can status change interrupt enable 0 no interrupt request is generated from this event. 1 a can status change event causes an error interrupt request. 5:4 rstate[1:0] receiver status change enable these rstat enable bits control the sensitivity level in which receiver state changes are causing cscif interrupts. independent of the chosen sensitivity level the rstat ?gs continue to indicate the actual receiver state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by receiver state changes. 01 generate cscif interrupt only if the receiver enters or leaves ?us-off?state. discard other receiver state changes for generating cscif interrupt. 10 generate cscif interrupt only if the receiver enters or leaves ?xerr?or ?us-off 2 state. discard other receiver state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 2 bus-off state is de?ed by the can standard (see bosch can 2.0a/b protocol speci?ation: for only transmitters. because the only possible state change for the transmitter from bus-off to txok also forces the receiver to skip its current state to rxok, the coding of the rxstat[1:0] ?gs de?e an additional bus-off state for the receiver (see section 12.3.4.1, ?scan receiver flag register (canrflg)?. 3:2 tstate[1:0] transmitter status change enable these tstat enable bits control the sensitivity level in which transmitter state changes are causing cscif interrupts. independent of the chosen sensitivity level, the tstat ?gs continue to indicate the actual transmitter state and are only updated if no cscif interrupt is pending. 00 do not generate any cscif interrupt caused by transmitter state changes. 01 generate cscif interrupt only if the transmitter enters or leaves ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 10 generate cscif interrupt only if the transmitter enters or leaves ?xerr?or ?us-off?state. discard other transmitter state changes for generating cscif interrupt. 11 generate cscif interrupt on all state changes. 1 ovrie overrun interrupt enable 0 no interrupt request is generated from this event. 1 an overrun event causes an error interrupt request. 0 rxfie receiver full interrupt enable 0 no interrupt request is generated from this event. 1 a receive buffer full (successful message reception) event causes a receiver interrupt request.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 233 note the cantflg register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: anytime write: anytime for txex ?gs when not in initialization mode; write of 1 clears ?g, write of 0 is ignored 12.3.7 mscan transmitter interrupt enable register (cantier) this register contains the interrupt enable bits for the transmit buffer empty interrupt ?gs. 76543210 r0 0 0 00 txe2 txe1 txe0 w reset: 00000111 = unimplemented figure 12-10. mscan transmitter flag register (cantflg) table 12-11. cantflg register field descriptions field description 2:0 txe[2:0] transmitter buffer empty this ?g indicates that the associated transmit message buffer is empty, and thus not scheduled for transmission. the cpu must clear the ?g after a message is set up in the transmit buffer and is due for transmission. the mscan sets the ?g after the message is sent successfully. the ?g is also set by the mscan when the transmission request is successfully aborted due to a pending abort request (see section 12.3.8, ?scan transmitter message abort request register (cantarq) ?. if not masked, a transmit interrupt is pending while this ?g is set. clearing a txex ?g also clears the corresponding abtakx (see section 12.3.9, ?scan transmitter message abort acknowledge register (cantaak) ?. when a txex ?g is set, the corresponding abtrqx bit is cleared (see section 12.3.8, ?scan transmitter message abort request register (cantarq) ?. when listen-mode is active (see section 12.3.2, ?scan control register 1 (canctl1) ? the txex ?gs cannot be cleared and no transmission is started. read and write accesses to the transmit buffer are blocked, if the corresponding txex bit is cleared (txex = 0) and the buffer is scheduled for transmission. 0 the associated message buffer is full (loaded with a message due for transmission) 1 the associated message buffer is empty (not scheduled) 76543210 r00000 txeie2 txeie1 txeie0 w reset: 00000000 = unimplemented figure 12-11. mscan transmitter interrupt enable register (cantier)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 234 freescale semiconductor note the cantier register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: anytime write: anytime when not in initialization mode 12.3.8 mscan transmitter message abort request register (cantarq) the cantarq register allows abort request of messages queued for transmission. note the cantarq register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: anytime write: anytime when not in initialization mode table 12-12. cantier register field descriptions field description 2:0 txeie[2:0] transmitter empty interrupt enable 0 no interrupt request is generated from this event. 1 a transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. see section 12.5.2.2, ?ransmit structures ?for details. 76543210 r00000 abtrq2 abtrq1 abtrq0 w reset: 00000000 = unimplemented figure 12-12. mscan transmitter message abort request register (cantarq) table 12-13. cantarq register field descriptions field description 2:0 abtrq[2:0] abort request ?the cpu sets the abtrqx bit to request that a scheduled message buffer (txex = 0) be aborted. the mscan grants the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). when a message is aborted, the associated txe (see section 12.3.6, ?scan transmitter flag register (cantflg) ? and abort acknowledge ?gs (abtak, see section 12.3.9, ?scan transmitter message abort acknowledge register (cantaak) ? are set and a transmit interrupt occurs if enabled. the cpu cannot reset abtrqx. abtrqx is reset whenever the associated txe ?g is set. 0 no abort request 1 abort request pending
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 235 12.3.9 mscan transmitter message abort acknowledge register (cantaak) the cantaak register indicates the successful abort of messages queued for transmission, if requested by the appropriate bits in the cantarq register. note the cantaak register is held in the reset state when the initialization mode is active (initrq = 1 and initak = 1). read: anytime write: unimplemented for abtakx ?gs 12.3.10 mscan transmit buffer selection register (cantbsel) the cantbsel selections of the actual transmit message buffer, which is accessible in the cantxfg register space. 76543210 r00000 abtak2 abtak1 abtak0 w reset: 00000000 = unimplemented figure 12-13. mscan transmitter message abort acknowledge register (cantaak) table 12-14. cantaak register field descriptions field description 2:0 abtak[2:0] abort acknowledge ?this ?g acknowledges that a message was aborted due to a pending transmission abort request from the cpu. after a particular message buffer is ?gged empty, this ?g can be used by the application software to identify whether the message was aborted successfully or was sent anyway. the abtakx ?g is cleared whenever the corresponding txe ?g is cleared. 0 the message was not aborted. 1 the message was aborted. 76543210 r00000 tx2 tx1 tx0 w reset: 00000000 = unimplemented figure 12-14. mscan transmit buffer selection register (cantbsel)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 236 freescale semiconductor note the cantbsel register is held in the reset state when the initialization mode is active (initrq = 1 and initak=1). this register is writable when not in initialization mode (initrq = 0 and initak = 0). read: find the lowest ordered bit set to 1, all other bits will be read as 0 write: anytime when not in initialization mode the following gives a short programming example of the usage of the cantbsel register: to get the next available transmit buffer, application software must read the cantflg register and write this value back into the cantbsel register. in this example tx buffers tx1 and tx2 are available. the value read from cantflg is therefore 0b0000_0110. when writing this value back to cantbsel, the tx buffer tx1 is selected in the cantxfg because the lowest numbered bit set to 1 is at bit position 1. reading back this value out of cantbsel results in 0b0000_0010, because only the lowest numbered bit position set to 1 is presented. this mechanism eases the application software the selection of the next available tx buffer. ldd cantflg; value read is 0b0000_0110 std cantbsel; value written is 0b0000_0110 ldd cantbsel; value read is 0b0000_0010 if all transmit message buffers are deselected, no accesses are allowed to the cantxfg buffer register. 12.3.11 mscan identi?r acceptance control register (canidac) the canidac register is used for identi?r ?ter acceptance control as described below. table 12-15. cantbsel register field descriptions field description 2:0 tx[2:0] transmit buffer select ?the lowest numbered bit places the respective transmit buffer in the cantxfg register space (e.g., tx1 = 1 and tx0 = 1 selects transmit buffer tx0; tx1 = 1 and tx0 = 0 selects transmit buffer tx1). read and write accesses to the selected transmit buffer will be blocked, if the corresponding txex bit is cleared and the buffer is scheduled for transmission (see section 12.3.6, ?scan transmitter flag register (cantflg)?. 0 the associated message buffer is deselected 1 the associated message buffer is selected, if lowest numbered bit 76543210 r0 0 idam1 idam0 0 idhit2 idhit1 idhit0 w reset: 00000000 = unimplemented figure 12-15. mscan identi?r acceptance control register (canidac)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 237 read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1), except bits idhitx, which are read-only the idhitx indicators are always related to the message in the foreground buffer (rxfg). when a message gets shifted into the foreground buffer of the receiver fifo the indicators are updated as well. 12.3.12 mscan miscellaneous register (canmisc) this register provides additional features. table 12-16. canidac register field descriptions field description 5:4 idam[1:0] identi?r acceptance mode the cpu sets these ?gs to de?e the identi?r acceptance ?ter organization (see section 12.5.3, ?denti?r acceptance filter ?. table 12-17 summarizes the different settings. in ?ter closed mode, no message is accepted such that the foreground buffer is never reloaded. 2:0 idhit[2:0] identi?r acceptance hit indicator ?the mscan sets these ?gs to indicate an identi?r acceptance hit (see section 12.5.3, ?denti?r acceptance filter ?. table 12-18 summarizes the different settings. table 12-17. identi?r acceptance mode settings idam1 idam0 identi?r acceptance mode 0 0 two 32-bit acceptance ?ters 0 1 four 16-bit acceptance ?ters 1 0 eight 8-bit acceptance ?ters 1 1 filter closed table 12-18. identi?r acceptance hit indication idhit2 idhit1 idhit0 identi?r acceptance hit 0 0 0 filter 0 hit 0 0 1 filter 1 hit 0 1 0 filter 2 hit 0 1 1 filter 3 hit 1 0 0 filter 4 hit 1 0 1 filter 5 hit 1 1 0 filter 6 hit 1 1 1 filter 7 hit
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 238 freescale semiconductor read: anytime write: anytime; write of ??clears ?g; write of ??ignored 12.3.13 mscan receive error counter (canrxerr) this register re?cts the status of the mscan receive error counter. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented note reading this register when in any other mode other than sleep or initialization mode may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. 76543210 r0000000 bohold w reset: 00000000 = unimplemented figure 12-16. mscan miscellaneous register (canmisc) table 12-19. canmisc register field descriptions field description 0 bohold bus-off state hold until user request ?if borm is set in section 12.3.2, ?scan control register 1 (canctl1), this bit indicates whether the module has entered the bus-off state. clearing this bit requests the recovery from bus-off. refer to section 12.6.2, ?us-off recovery ,?for details. 0 module is not bus-off or recovery has been requested by user in bus-off state 1 module is bus-off and holds this state until user request 76543210 r rxerr7 rxerr6 rxerr5 rxerr4 rxerr3 rxerr2 rxerr1 rxerr0 w reset: 00000000 = unimplemented figure 12-17. mscan receive error counter (canrxerr)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 239 12.3.14 mscan transmit error counter (cantxerr) this register re?cts the status of the mscan transmit error counter. read: only when in sleep mode (slprq = 1 and slpak = 1) or initialization mode (initrq = 1 and initak = 1) write: unimplemented note reading this register when in any other mode other than sleep or initialization mode, may return an incorrect value. for mcus with dual cpus, this may result in a cpu fault condition. writing to this register when in special modes can alter the mscan functionality. 12.3.15 mscan identi?r acceptance registers (canidar0-7) on reception, each message is written into the background receive buffer. the cpu is only signalled to read the message if it passes the criteria in the identi?r acceptance and identi?r mask registers (accepted); otherwise, the message is overwritten by the next message (dropped). the acceptance registers of the mscan are applied on the idr0?dr3 registers (see section 12.4.1, ?denti?r registers (idr0?dr3) ? of incoming messages in a bit by bit manner (see section 12.5.3, ?denti?r acceptance filter?. for extended identi?rs, all four acceptance and mask registers are applied. for standard identi?rs, only the ?st two (canidar0/1, canidmr0/1) are applied. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 76543210 r txerr7 txerr6 txerr5 txerr4 txerr3 txerr2 txerr1 txerr0 w reset: 00000000 = unimplemented figure 12-18. mscan transmit error counter (cantxerr) 76543210 r ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 w reset 0 0 0 0 0 0 0 0 figure 12-19. mscan identi?r acceptance registers (first bank) ?canidar0?anidar3
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 240 freescale semiconductor read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 12.3.16 mscan identi?r mask registers (canidmr0?anidmr7) the identi?r mask register speci?s which of the corresponding bits in the identi?r acceptance register are relevant for acceptance ?tering. to receive standard identi?rs in 32 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1 and canidmr5 to ?ont care. to receive standard identi?rs in 16 bit ?ter mode, it is required to program the last three bits (am[2:0]) in the mask registers canidmr1, canidmr3, canidmr5, and canidmr7 to ?ont care. read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) table 12-20. canidar0?anidar3 register field descriptions field description 7:0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. 76543210 r ac7ac6ac5ac4ac3ac2ac1ac0 w reset 00000000 figure 12-20. mscan identi?r acceptance registers (second bank) ?canidar4?anidar7 table 12-21. canidar4?anidar7 register field descriptions field description 7:0 ac[7:0] acceptance code bits ac[7:0] comprise a user-de?ed sequence of bits with which the corresponding bits of the related identi?r register (idrn) of the receive message buffer are compared. the result of this comparison is then masked with the corresponding identi?r mask register. 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 0 0 0 0 0 0 0 0 figure 12-21. mscan identi?r mask registers (first bank) ?canidmr0?anidmr3
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 241 read: anytime write: anytime in initialization mode (initrq = 1 and initak = 1) 12.4 programmers model of message storage the following section details the organization of the receive and transmit message buffers and the associated control registers. to simplify the programmer interface, the receive and transmit message buffers have the same outline. each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure. an additional transmit buffer priority register (tbpr) is de?ed for the transmit buffers. within the last two bytes of this memory map, the mscan stores a special 16-bit time stamp, which is sampled from an internal timer after successful transmission or reception of a message. this feature is only available for transmit and receiver buffers if the time bit is set (see section 12.3.1, ?scan control register 0 (canctl0)?. the time stamp register is written by the mscan. the cpu can only read these registers. table 12-22. canidmr0?anidmr3 register field descriptions field description 7:0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit (don? care) 76543210 r am7 am6 am5 am4 am3 am2 am1 am0 w reset 00000000 figure 12-22. mscan identi?r mask registers (second bank) ?canidmr4?anidmr7 table 12-23. canidmr4?anidmr7 register field descriptions field description 7:0 am[7:0] acceptance mask bits if a particular bit in this register is cleared, this indicates that the corresponding bit in the identi?r acceptance register must be the same as its identi?r bit before a match is detected. the message is accepted if all such bits match. if a bit is set, it indicates that the state of the corresponding bit in the identi?r acceptance register does not affect whether or not the message is accepted. 0 match corresponding acceptance code register and identi?r bits 1 ignore corresponding acceptance code register bit (don? care)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 242 freescale semiconductor figure 12-23 shows the common 13-byte data structure of receive and transmit buffers for extended identi?rs. the mapping of standard identi?rs into the idr registers is shown in figure 12-24 . all bits of the receive and transmit buffers are ??out of reset because of ram-based implementation 1 . all reserved or unused bits of the receive and transmit buffers always read ?? table 12-24. message buffer organization offset address register access 0x00x0 identi?r register 0 0x00x1 identi?r register 1 0x00x2 identi?r register 2 0x00x3 identi?r register 3 0x00x4 data segment register 0 0x00x5 data segment register 1 0x00x6 data segment register 2 0x00x7 data segment register 3 0x00x8 data segment register 4 0x00x9 data segment register 5 0x00xa data segment register 6 0x00xb data segment register 7 0x00xc data length register 0x00xd transmit buffer priority register 1 1 not applicable for receive buffers 0x00xe time stamp register (high byte) 2 2 read-only for cpu 0x00xf time stamp register (low byte) 3 3 read-only for cpu 1. exception: the transmit priority registers are 0 out of reset.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 243 read: for transmit buffers, anytime when txex ?g is set (see section 12.3.6, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see register name bit 7 654321 bit0 idr0 r id28 id27 id26 id25 id24 id23 id22 id21 w idr1 r id20 id19 id18 srr (1) 1 srr and ide are both 1s. ide (1) id17 id16 id15 w idr2 r id14 id13 id12 id11 id10 id9 id8 id7 w idr3 r id6 id5 id4 id3 id2 id1 id0 rtr 2 2 the position of rtr differs between extended and standard indenti?r mapping. w dsr0 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr1 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr2 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr3 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr4 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr5 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr6 r db7 db6 db5 db4 db3 db2 db1 db0 w dsr7 r db7 db6 db5 db4 db3 db2 db1 db0 w dlr r dlc3 dlc2 dlc1 dlc0 w = unused, always read ? figure 12-23. receive/transmit message buffer ?extended identi?r mapping
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 244 freescale semiconductor section 12.3.10, ?scan transmit buffer selection register (cantbsel) ?. for receive buffers, only when rxf ?g is set (see section 12.3.4.1, ?scan receiver flag register (canrflg) ?. write: for transmit buffers, anytime when txex ?g is set (see section 12.3.6, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 12.3.10, ?scan transmit buffer selection register (cantbsel) ?. unimplemented for receive buffers. reset: unde?ed (0x00xx) because of ram-based implementation 12.4.1 identi?r registers (idr0?dr3) the identi?r registers for an extended format identi?r consist of a total of 32 bits; id[28:0], srr, ide, and rtr bits. the identi?r registers for a standard format identi?r consist of a total of 13 bits; id[10:0], rtr, and ide bits. 12.4.1.1 idr0?dr3 for extended identi?r mapping register name bit 7 654321 bit 0 idr0 r id10 id9 id8 id7 id6 id5 id4 id3 w idr1 r id2 id1 id0 rtr 1 1 the position of rtr differs between extended and standard indenti?r mapping. ide 2 2 ide is 0. w idr2 r w idr3 r w = unused, always read ? figure 12-24. receive/transmit message buffer ?standard identi?r mapping 76543210 r id28 id27 id26 id25 id24 id23 id22 id21 w reset: xxxxxxxx figure 12-25. identi?r register 0 (idr0) ?extended identi?r mapping
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 245 table 12-25. idr0 register field descriptions ?extended field description 7:0 id[28:21] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 76543210 r id20 id19 id18 srr (1) 1 srr and ide are both 1s. ide (1) id17 id16 id15 w reset: xxxxxxxx figure 12-26. identi?r register 1 (idr1) ?extended identi?r mapping table 12-26. idr1 register field descriptions ?extended field description 7:5 id[20:18] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 4 srr substitute remote request ?this ?ed recessive bit is used only in extended format. it must be set to 1 by the user for transmission buffers and is stored as received on the can bus for receive buffers. 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit) 2:0 id[17:15] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 76543210 r id14 id13 id12 id11 id10 id9 id8 id7 w reset: xxxxxxxx figure 12-27. identi?r register 2 (idr2) ?extended identi?r mapping table 12-27. idr2 register field descriptions ?extended field description 7:0 id[14:7] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 246 freescale semiconductor 12.4.2 idr0?dr3 for standard identi?r mapping 76543210 r id6 id5 id4 id3 id2 id1 id0 rtr w reset: xxxxxxxx figure 12-28. identi?r register 3 (idr3) ?extended identi?r mapping table 12-28. idr3 register field descriptions ?extended field description 7:1 id[6:0] extended format identi?r the identi?rs consist of 29 bits (id[28:0]) for the extended format. id28 is the most signi?ant bit and is transmitted ?st on the can bus during the arbithation procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. 0 rtr remote transmission request ?this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame 76543210 r id10 id9 id8 id7 id6 id5 id4 id3 w reset: xxxxxxxx figure 12-29. identi?r register 0 ?standard mapping table 12-29. idr0 register field descriptions ?standard field description 7:0 id[10:3] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 12-30 . 76543210 r id2 id1 id0 rtr ide (1) 1 ide is 0. w reset: xxxxxxxx = unused; always read ? figure 12-30. identi?r register 1 ?standard mapping
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 247 12.4.3 data segment registers (dsr0-7) the eight data segment registers, each with bits db[7:0], contain the data to be transmitted or received. the number of bytes to be transmitted or received is determined by the data length code in the corresponding dlr register. table 12-30. idr1 register field descriptions field description 7:5 id[2:0] standard format identi?r the identi?rs consist of 11 bits (id[10:0]) for the standard format. id10 is the most signi?ant bit and is transmitted ?st on the can bus during the arbitration procedure. the priority of an identi?r is de?ed to be highest for the smallest binary number. see also id bits in table 12-29 . 4 rtr remote transmission request this ?g re?cts the status of the remote transmission request bit in the can frame. in the case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. in the case of a transmit buffer, this ?g de?es the setting of the rtr bit to be sent. 0 data frame 1 remote frame 3 ide id extended this ?g indicates whether the extended or standard identi?r format is applied in this buffer. in the case of a receive buffer, the ?g is set as received and indicates to the cpu how to process the buffer identi?r registers. in the case of a transmit buffer, the ?g indicates to the mscan what type of identi?r to send. 0 standard format (11 bit) 1 extended format (29 bit) 76543210 r w reset: xxxxxxxx = unused; always read ? figure 12-31. identi?r register 2 ?standard mapping 76543210 r w reset: xxxxxxxx = unused; always read ? figure 12-32. identi?r register 3 ?standard mapping
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 248 freescale semiconductor 12.4.4 data length register (dlr) this register keeps the data length ?ld of the can frame. 76543210 r db7 db6 db5 db4 db3 db2 db1 db0 w reset: xxxxxxxx figure 12-33. data segment registers (dsr0?sr7) ?extended identi?r mapping table 12-31. dsr0?sr7 register field descriptions field description 7:0 db[7:0] data bits 7:0 76543210 r dlc3 dlc2 dlc1 dlc0 w reset: xxxxxxxx = unused; always read ? figure 12-34. data length register (dlr) ?extended identi?r mapping table 12-32. dlr register field descriptions field description 3:0 dlc[3:0] data length code bits the data length code contains the number of bytes (data byte count) of the respective message. during the transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted data bytes is always 0. the data byte count ranges from 0 to 8 for a data frame. table 12-33 shows the effect of setting the dlc bits.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 249 12.4.5 transmit buffer priority register (tbpr) this register de?es the local priority of the associated message transmit buffer. the local priority is used for the internal prioritization process of the mscan and is de?ed to be highest for the smallest binary number. the mscan implements the following internal prioritization mechanisms: all transmission buffers with a cleared txex ?g participate in the prioritization immediately before the sof (start of frame) is sent. the transmission buffer with the lowest local priority ?ld wins the prioritization. in cases of more than one buffer having the same lowest priority, the message buffer with the lower index number wins. read: anytime when txex ?g is set (see section 12.3.6, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 12.3.10, ?scan transmit buffer selection register (cantbsel) ?. write: anytime when txex ?g is set (see section 12.3.6, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 12.3.10, ?scan transmit buffer selection register (cantbsel) ?. 12.4.6 time stamp register (tsrh?srl) if the time bit is enabled, the mscan will write a time stamp to the respective registers in the active transmit or receive buffer as soon as a message has been acknowledged on the can bus (see table 12-33. data length codes data length code data byte count dlc3 dlc2 dlc1 dlc0 00000 00011 00102 00113 01004 01015 01106 01117 10008 76543210 r prio7 prio6 prio5 prio4 prio3 prio2 prio1 prio0 w reset: 00000000 figure 12-35. transmit buffer priority register (tbpr)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 250 freescale semiconductor section 12.3.1, ?scan control register 0 (canctl0) ?. in case of a transmission, the cpu can only read the time stamp after the respective transmit buffer has been ?gged empty. the timer value, which is used for stamping, is taken from a free running internal can bit clock. a timer overrun is not indicated by the mscan. the timer is reset (all bits set to 0) during initialization mode. the cpu can only read the time stamp registers. read: anytime when txex ?g is set (see section 12.3.6, ?scan transmitter flag register (cantflg) ? and the corresponding transmit buffer is selected in cantbsel (see section 12.3.10, ?scan transmit buffer selection register (cantbsel) ?. write: unimplemented 12.5 functional description 12.5.1 general this section provides a complete functional description of the mscan. it describes each of the features and modes listed in the introduction. 76543210 r tsr15 tsr14 tsr13 tsr12 tsr11 tsr10 tsr9 tsr8 w reset: xxxxxxxx figure 12-36. time stamp register ?high byte (tsrh) 76543210 r tsr7 tsr6 tsr5 tsr4 tsr3 tsr2 tsr1 tsr0 w reset: xxxxxxxx figure 12-37. time stamp register ?low byte (tsrl)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 251 12.5.2 message storage figure 12-38. user model for message buffer organization mscan facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. mscan rx0 rx1 can receive / transmit engine cpu12 memory mapped i/o cpu bus mscan tx2 txe2 prio receiver transmitter rxbg txbg tx0 txe0 prio txbg tx1 prio txe1 txfg cpu bus rx2 rx3 rx4 rxf rxfg
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 252 freescale semiconductor 12.5.2.1 message transmit background modern application layer software is built upon two fundamental assumptions: any can node is able to send out a stream of scheduled messages without releasing the can bus between the two messages. such nodes arbitrate for the can bus immediately after sending the previous message and only release the can bus in case of lost arbitration. the internal message queue within any can node is organized such that the highest priority message is sent out ?st, if more than one message is ready to be sent. the behavior described in the bullets above cannot be achieved with a single transmit buffer. that buffer must be reloaded immediately after the previous message is sent. this loading process lasts a ?ite amount of time and must be completed within the inter-frame sequence (ifs) to be able to send an uninterrupted stream of messages. even if this is feasible for limited can bus speeds, it requires that the cpu reacts with short latencies to the transmit interrupt. a double buffer scheme de-couples the reloading of the transmit buffer from the actual message sending and, therefore, reduces the reactiveness requirements of the cpu. problems can arise if the sending of a message is ?ished while the cpu re-loads the second buffer. no buffer would then be ready for transmission, and the can bus would be released. at least three transmit buffers are required to meet the ?st of the above requirements under all circumstances. the mscan has three transmit buffers. the second requirement calls for some sort of internal prioritization which the mscan implements with the ?ocal priority?concept described in section 12.5.2.2, ?ransmit structures . 12.5.2.2 transmit structures the mscan triple transmit buffer scheme optimizes real-time performance by allowing multiple messages to be set up in advance. the three buffers are arranged as shown in figure 12-38 . all three buffers have a 13-byte data structure similar to the outline of the receive buffers (see section 12.4, ?rogrammers model of message storage ?. an additional section 12.4.5, ?ransmit buffer priority register (tbpr) contains an 8-bit local priority ?ld (prio) (see section 12.4.5, ?ransmit buffer priority register (tbpr) ?. the remaining two bytes are used for time stamping of a message, if required (see section 12.4.6, ?ime stamp register (tsrh?srl) ?. to transmit a message, the cpu must identify an available transmit buffer, which is indicated by a set transmitter buffer empty (txex) ?g (see section 12.3.6, ?scan transmitter flag register (cantflg) ?. if a transmit buffer is available, the cpu must set a pointer to this buffer by writing to the cantbsel register (see section 12.3.10, ?scan transmit buffer selection register (cantbsel) ?. this makes the respective buffer accessible within the cantxfg address space (see section 12.4, ?rogrammers model of message storage ?. the algorithmic feature associated with the cantbsel register simpli?s the transmit buffer selection. in addition, this scheme makes the handler software simpler because only one address area is applicable for the transmit process, and the required address space is minimized. the cpu then stores the identi?r, the control bits, and the data content into one of the transmit buffers. finally, the buffer is ?gged as ready for transmission by clearing the associated txe ?g.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 253 the mscan then schedules the message for transmission and signals the successful transmission of the buffer by setting the associated txe ?g. a transmit interrupt (see section 12.5.7.2, ?ransmit interrupt ? is generated 1 when txex is set and can be used to drive the application software to re-load the buffer. if more than one buffer is scheduled for transmission when the can bus becomes available for arbitration, the mscan uses the local priority setting of the three buffers to determine the prioritization. for this purpose, every transmit buffer has an 8-bit local priority ?ld (prio). the application software programs this ?ld when the message is set up. the local priority re?cts the priority of this particular message relative to the set of messages being transmitted from this node. the lowest binary value of the prio ?ld is de?ed to be the highest priority. the internal scheduling process takes place whenever the mscan arbitrates for the can bus. this is also the case after the occurrence of a transmission error. when a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message in one of the three transmit buffers. because messages that are already in transmission cannot be aborted, the user must request the abort by setting the corresponding abort request bit (abtrq) (see section 12.3.8, ?scan transmitter message abort request register (cantarq) ?) the mscan then grants the request, if possible, by: 1. setting the corresponding abort acknowledge ?g (abtak) in the cantaak register. 2. setting the associated txe ?g to release the buffer. 3. generating a transmit interrupt. the transmit interrupt handler software can determine from the setting of the abtak ?g whether the message was aborted (abtak = 1) or sent (abtak = 0). 12.5.2.3 receive structures the received messages are stored in a ve stage input fifo. the ve message buffers are alternately mapped into a single memory area (see figure 12-38 ). the background receive buffer (rxbg) is exclusively associated with the mscan, but the foreground receive buffer (rxfg) is addressable by the cpu (see figure 12-38 ). this scheme simpli?s the handler software because only one address area is applicable for the receive process. all receive buffers have a size of 15 bytes to store the can control bits, the identi?r (standard or extended), the data contents, and a time stamp, if enabled (see section 12.4, ?rogrammers model of message storage?. the receiver full ?g (rxf) (see section 12.3.4.1, ?scan receiver flag register (canrflg) ? signals the status of the foreground receive buffer. when the buffer contains a correctly received message with a matching identi?r, this ?g is set. on reception, each message is checked to see whether it passes the ?ter (see section 12.5.3, ?denti?r acceptance filter ? and simultaneously is written into the active rxbg. after successful reception of a valid message, the mscan shifts the content of rxbg into the receiver fifo 2 , sets the rxf ?g, and generates a receive interrupt (see section 12.5.7.3, ?eceive interrupt ? to the cpu 3 . the users receive handler must read the received message from the rxfg and then reset the rxf ?g to acknowledge the interrupt and to release the foreground buffer. a new message, which can follow immediately after the ifs 1. the transmit interrupt occurs only if not masked. a polling scheme can be applied on txex also. 2. only if the rxf ?g is not set. 3. the receive interrupt occurs only if not masked. a polling scheme can be applied on rxf also.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 254 freescale semiconductor ?ld of the can frame, is received into the next available rxbg. if the mscan receives an invalid message in its rxbg (wrong identi?r, transmission errors, etc.) the actual contents of the buffer will be over-written by the next message. the buffer will then not be shifted into the fifo. when the mscan module is transmitting, the mscan receives its own transmitted messages into the background receive buffer, rxbg, but does not shift it into the receiver fifo, generate a receive interrupt, or acknowledge its own messages on the can bus. the exception to this rule is in loopback mode (see section 12.3.2, ?scan control register 1 (canctl1) ? where the mscan treats its own messages exactly like all other incoming messages. the mscan receives its own transmitted messages in the event that it loses arbitration. if arbitration is lost, the mscan must be prepared to become a receiver. an overrun condition occurs when all receive message buffers in the fifo are ?led with correctly received messages with accepted identi?rs and another message is correctly received from the can bus with an accepted identi?r. the latter message is discarded and an error interrupt with overrun indication is generated if enabled (see section 12.5.7.5, ?rror interrupt ?. the mscan remains able to transmit messages while the receiver fifo is full, but all incoming messages are discarded. as soon as a receive buffer in the fifo is available again, new valid messages will be accepted. 12.5.3 identi?r acceptance filter the mscan identi?r acceptance registers (see section 12.3.11, ?scan identi?r acceptance control register (canidac) ? de?e the acceptable patterns of the standard or extended identi?r (id[10:0] or id[28:0]). any of these bits can be marked ?ont care?in the mscan identi?r mask registers (see section 12.3.16, ?scan identi?r mask registers (canidmr0?anidmr7) ?. a ?ter hit is indicated to the application software by a set receive buffer full ?g (rxf = 1) and three bits in the canidac register (see section 12.3.11, ?scan identi?r acceptance control register (canidac) ?. these identi?r hit ?gs (idhit[2:0]) clearly identify the ?ter section that caused the acceptance. they simplify the application softwares task to identify the cause of the receiver interrupt. if more than one hit occurs (two or more ?ters match), the lower hit has priority. a very ?xible programmable generic identi?r acceptance ?ter has been introduced to reduce the cpu interrupt loading. the ?ter is programmable to operate in four different modes (see bosch can 2.0a/b protocol speci?ation): two identi?r acceptance ?ters, each to be applied to: the full 29 bits of the extended identi?r and to the following bits of the can 2.0b frame: remote transmission request (rtr) identi?r extension (ide) substitute remote request (srr) the 11 bits of the standard identi?r plus the rtr and ide bits of the can 2.0a/b messages 1 . this mode implements two ?ters for a full length can 2.0b compliant extended identi?r. figure 12-39 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces a ?ter 0 hit. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces a ?ter 1 hit. 1.although this mode can be used for standard identifiers, it is recommended to use the four or eight identifier acceptance filters for standard identifiers
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 255 four identi?r acceptance ?ters, each to be applied to a) the 14 most signi?ant bits of the extended identi?r plus the srr and ide bits of can 2.0b messages or b) the 11 bits of the standard identi?r, the rtr and ide bits of can 2.0a/b messages. figure 12-40 shows how the ?st 32-bit ?ter bank (canidar0?anida3, canidmr0?canidmr) produces ?ter 0 and 1 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 2 and 3 hits. eight identi?r acceptance ?ters, each to be applied to the ?st 8 bits of the identi?r. this mode implements eight independent ?ters for the ?st 8 bits of a can 2.0a/b compliant standard identi?r or a can 2.0b compliant extended identi?r. figure 12-41 shows how the ?st 32-bit ?ter bank (canidar0?anidar3, canidmr0?anidmr3) produces ?ter 0 to 3 hits. similarly, the second ?ter bank (canidar4?anidar7, canidmr4?anidmr7) produces ?ter 4 to 7 hits. closed ?ter. no can message is copied into the foreground buffer rxfg, and the rxf ?g is never set. figure 12-39. 32-bit maskable identi?r acceptance filter id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 0 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 256 freescale semiconductor figure 12-40. 16-bit maskable identi?r acceptance filters id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 canidar0 am7 am0 canidmr0 ac7 ac0 canidar1 am7 am0 canidmr1 id accepted (filter 0 hit) ac7 ac0 canidar2 am7 am0 canidmr2 ac7 ac0 canidar3 am7 am0 canidmr3 id accepted (filter 1 hit) can 2.0b extended identi?r can 2.0a/b standard identi?r
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 257 figure 12-41. 8-bit maskable identi?r acceptance filters mscan ?ter uses three sets of registers to provide the ?ter con?uration. firstly, the canidac register determines the con?uration of the banks into ?ter sizes and number of ?ters. secondly, registers canidmr0/1/2/3 determine those bits on which the ?ter will operate by placing a ? at the appropriate can 2.0b extended identi?r can 2.0a/b standard identi?r ac7 ac0 cidar3 am7 am0 cidmr3 id accepted (filter 3 hit) ac7 ac0 cidar2 am7 am0 cidmr2 id accepted (filter 2 hit) ac7 ac0 cidar1 am7 am0 cidmr1 id accepted (filter 1 hit) id28 id21 idr0 id10 id3 idr0 id20 id15 idr1 id2 ide idr1 id14 id7 idr2 id10 id3 idr2 id6 rtr idr3 id10 id3 idr3 ac7 ac0 cidar0 am7 am0 cidmr0 id accepted (filter 0 hit)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 258 freescale semiconductor bit position in the ?ter register. finally, registers canidar0/1/2/3 determine the value of those bits determined by canidmr0/1/2/3. for instance in the case of the ?ter value of: 0001x1001x0 the canidmr0/1/2/3 register would be con?ured as: 00001000010 and so all message identi?r bits except bit 1 and bit 6 would be compared against the canidar0/1/2/3 registers. these would be con?ured as: 00010100100 in this case bits 1 and 6 are set to ?? but since they are ignored it is equally valid to set them to ?? 12.5.3.1 identi?r acceptance filters example as described above, ?ters work by comparisons to individual bits in the can message identi?r ?ld. the ?ter will check each one of the eleven bits of a standard can message identi?r. suppose a ?ter value of 0001x1001x0. in this simple example, there are only three possible can messages. filter value: 0001x1001x0 message 1: 00011100110 message 2: 00110100110 message 3: 00010100100 message 2 will be rejected since its third most signi?ant bit is not ??- 001. the ?ter is simply a convenient way of de?ing the set of messages that the cpu must receive. for full 29-bits of an extended can message identi?r, the ?ter identi?s two sets of messages: one set that it receives and one set that it rejects. alternatively, the ?ter may be split into two. this allows the mscan to examine only the ?st 16 bits of a message identi?r, but allows two separate ?ters to perform the checking. see the example below: filter value a: 0001x1001x0 filter value b: 00x101x01x0 message 1: 00011100110 message 2: 00110100110 message 3: 00010100100 mscan will accept all three messages. filter a will accept messages 1 and 3 as before and ?ter b will accept message 2. in practice, it is unimportant which ?ter accepts the message - messages accepted by either will be placed in the input buffer. a message may be accepted by more than one ?ter.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 259 12.5.3.2 protocol violation protection the mscan protects the user from accidentally violating the can protocol through programming errors. the protection logic implements the following features: the receive and transmit error counters cannot be written or otherwise manipulated. all registers which control the con?uration of the mscan cannot be modi?d while the mscan is on-line. the mscan has to be in initialization mode. the corresponding initrq/initak handshake bits in the canctl0/canctl1 registers (see section 12.3.1, ?scan control register 0 (canctl0) ? serve as a lock to protect the following registers: mscan control 1 register (canctl1) mscan bus timing registers 0 and 1 (canbtr0, canbtr1) mscan identi?r acceptance control register (canidac) mscan identi?r acceptance registers (canidar0?anidar7) mscan identi?r mask registers (canidmr0?anidmr7) the txcan pin is immediately forced to a recessive state when the mscan goes into the power down mode or initialization mode (see section 12.5.5.6, ?scan power down mode ,?and section 12.5.5.5, ?scan initialization mode ?. the mscan enable bit (cane) is writable only once in normal system operation modes, which provides further protection against inadvertently disabling the mscan. 12.5.3.3 clock system figure 12-42 shows the structure of the mscan clock generation circuitry. figure 12-42. mscan clocking scheme the clock source bit (clksrc) in the canctl1 register ( 12.3.2/-226) de?es whether the internal canclk is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock. the clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the can protocol are met. additionally, for high can bus rates (1 mbps), a 45% to 55% duty cycle of the clock is required. bus clock oscillator clock mscan canclk clksrc clksrc prescaler (1 .. 64) time quanta clock (tq)
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 260 freescale semiconductor if the bus clock is generated from a pll, it is recommended to select the oscillator clock rather than the bus clock due to jitter considerations, especially at the faster can bus rates. pll lock may also be too wide to ensure adequate clock tolerance. for microcontrollers without a clock and reset generator (crg), canclk is driven from the crystal oscillator (oscillator clock). a programmable prescaler generates the time quanta (tq) clock from canclk. a time quantum is the atomic unit of time handled by the mscan. eqn. 12-2 a bit time is subdivided into three segments as described in the bosch can speci?ation. (see figure 12-43 ): sync_seg: this segment has a ?ed length of one time quantum. signal edges are expected to happen within this section. time segment 1: this segment includes the prop_seg and the phase_seg1 of the can standard. it can be programmed by setting the parameter tseg1 to consist of 4 to 16 time quanta. time segment 2: this segment represents the phase_seg2 of the can standard. it can be programmed by setting the tseg2 parameter to be 2 to 8 time quanta long. eqn. 12-3 figure 12-43. segments within the bit time tq f canclk prescaler value ( ) ---------------------------------------------------- -- = bit rate f tq number of time quanta () -------------------------------------------------------------------------------- - = sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + phase_seg1) (phase_seg2) transmit point
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 261 the synchronization jump width (see the bosch can speci?ation for details) can be programmed in a range of 1 to 4 time quanta by setting the sjw parameter. the sync_seg, tseg1, tseg2, and sjw parameters are set by programming the mscan bus timing registers (canbtr0, canbtr1) (see section 12.3.3, ?scan bus timing register 0 (canbtr0) and section 12.3.4, ?scan bus timing register 1 (canbtr1) ?. table 12-35 gives an overview of the can compliant segment settings and the related parameter values. note it is the users responsibility to ensure the bit time settings are in compliance with the can standard. 12.5.4 modes of operation 12.5.4.1 normal modes the mscan module behaves as described within this speci?ation in all normal system operation modes. 12.5.4.2 special modes the mscan module behaves as described within this speci?ation in all special system operation modes. table 12-34. time segment syntax syntax description sync_seg system expects transitions to occur on the can bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node in receive mode samples the can bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 12-35. can standard compliant bit time segment settings time segment 1 tseg1 time segment 2 tseg2 synchronization jump width sjw 5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1 4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2 5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3 6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3 7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3 8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3 9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 262 freescale semiconductor 12.5.4.3 emulation modes in all emulation modes, the mscan module behaves just like normal system operation modes as described within this speci?ation. 12.5.4.4 listen-only mode in an optional can bus monitoring mode (listen-only), the can node is able to receive valid data frames and valid remote frames, but it sends only ?ecessive?bits on the can bus. in addition, it cannot start a transmision. if the mac sub-layer is required to send a ?ominant bit (ack bit, overload ?g, or active error ?g), the bit is rerouted internally so that the mac sub-layer monitors this ?ominant bit, although the can bus may remain in recessive state externally. 12.5.4.5 security modes the mscan module has no security features. 12.5.4.6 loopback self test mode loopback self test mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. in this mode, the transmitter output is internally connected to the receiver input. the rxcan input pin is ignored and the txcan output goes to the recessive state (logic 1). the mscan behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. in this state, the mscan ignores the bit sent during the ack slot in the can frame acknowledge ?ld to ensure proper reception of its own message. both transmit and receive interrupts are generated. 12.5.5 low-power options if the mscan is disabled (cane = 0), the mscan clocks are stopped for power saving. if the mscan is enabled (cane = 1), the mscan has two additional modes with reduced power consumption, compared to normal mode: sleep and power down mode. in sleep mode, power consumption is reduced by stopping all clocks except those to access the registers from the cpu side. in power down mode, all clocks are stopped and no power is consumed. table 12-36 summarizes the combinations of mscan and cpu modes. a particular combination of modes is entered by the given settings on the cswai and slprq/slpak bits. for all modes, an mscan wake-up interrupt can occur only if the mscan is in sleep mode (slprq = 1 and slpak = 1), wake-up functionality is enabled (wupe = 1), and the wake-up interrupt is enabled (wupie = 1).
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 263 12.5.5.1 operation in run mode as shown in table 12-36 , only mscan sleep mode is available as low power option when the cpu is in run mode. 12.5.5.2 operation in wait mode the wait instruction puts the mcu in a low power consumption stand-by mode. if the cswai bit is set, additional power can be saved in power down mode because the cpu clocks are stopped. after leaving this power down mode, the mscan restarts its internal controllers and enters normal mode again. while the cpu is in wait mode, the mscan can be operated in normal mode and generate interrupts (registers can be accessed via background debug mode). the mscan can also operate in any of the low-power modes depending on the values of the slprq/slpak and cswai bits as seen in table 12-36 . 12.5.5.3 operation in stop mode the stop instruction puts the mcu in a low power consumption stand-by mode. in stop1 or stop2 modes, the mscan is set in power down mode regardless of the value of the slprq/slpak. in stop3 mode, power down or sleep modes are determined by the slprq/slpak values set prior to entering stop3. cswai bit has no function in any of the stop modes. table 12-36 . table 12-36. cpu vs. mscan operating modes cpu mode mscan mode normal reduced power consumption sleep power down disabled (cane=0) run cswai = x 1 slprq = 0 slpak = 0 1 ??means don? care. cswai = x slprq = 1 slpak = 1 cswai = x slprq = x slpak = x wait cswai = 0 slprq = 0 slpak = 0 cswai = 0 slprq = 1 slpak = 1 cswai = 1 slprq = x slpak = x cswai = x slprq = x slpak = x stop3 cswai = x 2 slprq = 1 slpak = 1 2 for a safe wake up from sleep mode, slprq and slpak must be set to 1 before going into stop3 mode. cswai = x slprq = 0 slpak = 0 cswai = x slprq = x slpak = x stop1 or 2 cswai = x slprq = x slpak = x cswai = x slprq = x slpak = x
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 264 freescale semiconductor 12.5.5.4 mscan sleep mode the cpu can request the mscan to enter this low power mode by asserting the slprq bit in the canctl0 register. the time when the mscan enters sleep mode depends on a ?ed synchronization delay and its current activity: if there are one or more message buffers scheduled for transmission (txex = 0), the mscan will continue to transmit until all transmit message buffers are empty (txex = 1, transmitted successfully or aborted) and then goes into sleep mode. if the mscan is receiving, it continues to receive and goes into sleep mode as soon as the can bus next becomes idle. if the mscan is neither transmitting nor receiving, it immediately goes into sleep mode. figure 12-44. sleep request / acknowledge cycle note the application software must avoid setting up a transmission (by clearing one or more txex ?g(s)) and immediately request sleep mode (by setting slprq). whether the mscan starts transmitting or goes into sleep mode directly depends on the exact sequence of operations. if sleep mode is active, the slprq and slpak bits are set ( figure 12-44 ). the application software must use slpak as a handshake indication for the request (slprq) to go into sleep mode. when in sleep mode (slprq = 1 and slpak = 1), the mscan stops its internal clocks. however, clocks that allow register accesses from the cpu side continue to run. if the mscan is in bus-off state, it stops counting the 128 occurrences of 11 consecutive recessive bits due to the stopped clocks. the txcan pin remains in a recessive state. if rxf = 1, the message can be read and rxf can be cleared. shifting a new message into the foreground buffer of the receiver fifo (rxfg) does not take place while in sleep mode. it is possible to access the transmit buffers and to clear the associated txe ?gs. no message abort takes place while in sleep mode. sync sync bus cloc k domain can cloc k domain mscan in sleep mode cpu sleep request slprq flag slpak flag slprq sync. slpak sync. slprq slpak
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 265 if the wupe bit in canclt0 is not asserted, the mscan will mask any activity it detects on can. the rxcan pin is therefore held internally in a recessive state. this locks the mscan in sleep mode ( figure 12-45 ). wupe must be set before entering sleep mode to take effect.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 266 freescale semiconductor the mscan is able to leave sleep mode (wake up) only when: can bus activity occurs and wupe = 1 or the cpu clears the slprq bit note the cpu cannot clear the slprq bit before sleep mode (slprq = 1 and slpak = 1) is active. after wake-up, the mscan waits for 11 consecutive recessive bits to synchronize to the can bus. as a consequence, if the mscan is woken-up by a can frame, this frame is not received. the receive message buffers (rxfg and rxbg) contain messages if they were received before sleep mode was entered. all pending actions will be executed upon wake-up; copying of rxbg into rxfg, message aborts and message transmissions. if the mscan remains in bus-off state after sleep mode was exited, it continues counting the 128 occurrences of 11 consecutive recessive bits. figure 12-45. simpli?d state transitions for entering/leaving sleep mode wait idle tx/rx message active can activity can activity & sleep slprq startup for idle (can activity & wupe) | (can activity & wupe) | slprq can activity can activity can activity & can activity slprq slprq can activity
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 267 12.5.5.5 mscan initialization mode in initialization mode, any on-going transmission or reception is immediately aborted and synchronization to the can bus is lost, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations, the mscan immediately drives the txcan pin into a recessive state. note the user is responsible for ensuring that the mscan is not active when initialization mode is entered. the recommended procedure is to bring the mscan into sleep mode (slprq = 1 and slpak = 1) before setting the initrq bit in the canctl0 register. otherwise, the abort of an on-going message can cause an error condition and can impact other can bus devices. in initialization mode, the mscan is stopped. however, interface registers remain accessible. this mode is used to reset the canctl0, canrflg, canrier, cantflg, cantier, cantarq, cantaak, and cantbsel registers to their default values. in addition, the mscan enables the con?uration of the canbtr0, canbtr1 bit timing registers; canidac; and the canidar, canidmr message ?ters. see section 12.3.1, ?scan control register 0 (canctl0) , for a detailed description of the initialization mode. figure 12-46. initialization request/acknowledge cycle due to independent clock domains within the mscan, initrq must be synchronized to all domains by using a special handshake mechanism. this handshake causes additional synchronization delay (see section figure 12-46., ?nitialization request/acknowledge cycle ?. if there is no message transfer ongoing on the can bus, the minimum delay will be two additional bus clocks and three additional can clocks. when all parts of the mscan are in initialization mode, the initak ?g is set. the application software must use initak as a handshake indication for the request (initrq) to go into initialization mode. note the cpu cannot clear initrq before initialization mode (initrq = 1 and initak = 1) is active. sync sync bus cloc k domain can cloc k domain cpu init request init flag initak flag initrq sync. initak sync. initrq initak
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 268 freescale semiconductor 12.5.5.6 mscan power down mode the mscan is in power down mode ( table 12-36 ) when cpu is in stop mode or cpu is in wait mode and the cswai bit is set when entering the power down mode, the mscan immediately stops all ongoing transmissions and receptions, potentially causing can protocol violations. to protect the can bus system from fatal consequences of violations to the above rule, the mscan immediately drives the txcan pin into a recessive state. note the user is responsible for ensuring that the mscan is not active when power down mode is entered. the recommended procedure is to bring the mscan into sleep mode before the stop or wait instruction (if cswai is set) is executed. otherwise, the abort of an ongoing message can cause an error condition and impact other can bus devices. in power down mode, all clocks are stopped and no registers can be accessed. if the mscan was not in sleep mode before power down mode became active, the module performs an internal recovery cycle after powering up. this causes some ?ed delay before the module enters normal mode again. 12.5.5.7 programmable wake-up function the mscan can be programmed to wake up the mscan as soon as can bus activity is detected (see control bit wupe in section 12.3.1, ?scan control register 0 (canctl0) ?. the sensitivity to existing can bus action can be modi?d by applying a low-pass ?ter function to the rxcan input line while in sleep mode (see control bit wupm in section 12.3.2, ?scan control register 1 (canctl1)?. this feature can be used to protect the mscan from wake-up due to short glitches on the can bus lines. such glitches can result from?or example?lectromagnetic interference within noisy environments. 12.5.6 reset initialization the reset state of each individual bit is listed in section 12.3, ?egister de?ition ,?which details all the registers and their bit-?lds. 12.5.7 interrupts this section describes all interrupts originated by the mscan. it documents the enable bits and generated ?gs. each interrupt is listed and described separately.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 269 12.5.7.1 description of interrupt operation the mscan supports four interrupt vectors (see table 12-37 ), any of which can be individually masked (for details see sections from section 12.3.5, ?scan receiver interrupt enable register (canrier) , to section 12.3.7, ?scan transmitter interrupt enable register (cantier) ?. note the dedicated interrupt vector addresses are de?ed in the resets and interrupts chapter. 12.5.7.2 transmit interrupt at least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. the txex ?g of the empty message buffer is set. 12.5.7.3 receive interrupt a message is successfully received and shifted into the foreground buffer (rxfg) of the receiver fifo. this interrupt is generated immediately after receiving the eof symbol. the rxf ?g is set. if there are multiple messages in the receiver fifo, the rxf ?g is set as soon as the next message is shifted to the foreground buffer. 12.5.7.4 wake-up interrupt a wake-up interrupt is generated if activity on the can bus occurs during mscan internal sleep mode. wupe (see section 12.3.1, ?scan control register 0 (canctl0) ? must be enabled. 12.5.7.5 error interrupt an error interrupt is generated if an overrun of the receiver fifo, error, warning, or bus-off condition occurrs. section 12.3.4.1, ?scan receiver flag register (canrflg) indicates one of the following conditions: overrun an overrun condition of the receiver fifo as described in section 12.5.2.3, ?eceive structures ,?occurred. can status change ?the actual value of the transmit and receive error counters control the can bus state of the mscan. as soon as the error counters skip into a critical range (tx/rx-warning, tx/rx-error, bus-off) the mscan ?gs an error condition. the status change, which caused the error condition, is indicated by the tstat and rstat ?gs (see table 12-37. interrupt vectors interrupt source ccr mask local enable wake-up interrupt (wupif) i bit canrier (wupie) error interrupts interrupt (cscif, ovrif) i bit canrier (cscie, ovrie) receive interrupt (rxf) i bit canrier (rxfie) transmit interrupts (txe[2:0]) i bit cantier (txeie[2:0])
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 270 freescale semiconductor section 12.3.4.1, ?scan receiver flag register (canrflg) ?and section 12.3.5, ?scan receiver interrupt enable register (canrier) ?. 12.5.7.6 interrupt acknowledge interrupts are directly associated with one or more status ?gs in either the section 12.3.4.1, ?scan receiver flag register (canrflg) ?or the section 12.3.6, ?scan transmitter flag register (cantflg) .?interrupts are pending as long as one of the corresponding ?gs is set. the ?gs in canrflg and cantflg must be reset within the interrupt handler to handshake the interrupt. the ?gs are reset by writing a 1 to the corresponding bit position. a ?g cannot be cleared if the respective condition prevails. note it must be guaranteed that the cpu clears only the bit causing the current interrupt. for this reason, bit manipulation instructions (bset) must not be used to clear interrupt ?gs. these instructions may cause accidental clearing of interrupt ?gs which are set after entering the current interrupt service routine. 12.5.7.7 recovery from stop or wait the mscan can recover from stop or wait via the wake-up interrupt. this interrupt can only occur if the mscan was in sleep mode (slprq = 1 and slpak = 1) before entering power down mode, the wake-up option is enabled (wupe = 1), and the wake-up interrupt is enabled (wupie = 1). 12.6 initialization/application information 12.6.1 mscan initialization the procedure to initially start up the mscan module out of reset is as follows: 1. assert cane 2. write to the con?uration registers in initialization mode 3. clear initrq to leave initialization mode and enter normal mode if the con?uration of registers which are writable in initialization mode needs to be changed only when the mscan module is in normal mode: 1. bring the module into sleep mode by setting slprq and awaiting slpak to assert after the can bus becomes idle. 2. enter initialization mode: assert initrq and await initak 3. write to the con?uration registers in initialization mode 4. clear initrq to leave initialization mode and continue in normal mode
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 271 12.6.2 bus-off recovery the bus-off recovery is user con?urable. the bus-off state can either be exited automatically or on user request. for reasons of backwards compatibility, the mscan defaults to automatic recovery after reset. in this case, the mscan will become error active again after counting 128 occurrences of 11 consecutive recessive bits on the can bus (see the bosch can speci?ation for details). if the mscan is con?ured for user request (borm set in section 12.3.2, ?scan control register 1 (canctl1) ?, the recovery from bus-off starts after both independent events have become true: 128 occurrences of 11 consecutive recessive bits on the can bus have been monitored bohold in section 12.3.12, ?scan miscellaneous register (canmisc) has been cleared by the user these two events may occur in any order.
chapter 12 freescales controller area network (s08mscanv1) mc9s08de60 series data sheet, rev. 3 272 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 273 chapter 13 serial peripheral interface (s08spiv3) 13.1 introduction the serial peripheral interface (spi) module provides for full-duplex, synchronous, serial communication between the mcu and peripheral devices. these peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, memories, etc. the spi runs at a baud rate up to the bus clock divided by two in master mode and bus clock divided by four in slave mode. all devices in the mc9s08de60 series mcus contain one spi module, as shown in the following block diagram. note ensure that the spi should not be disabled (spe=0) at the same time as a bit change to the cpha bit. these changes should be performed as separate operations or unexpected behavior may occur.
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 274 freescale semiconductor figure 13-1. mc9s08de60/32 block diagram emphasizing the spi block and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte1/rxd1 pte0/txd1 pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s088de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k serial peripheral interface module (spi) miso ss spsck mosi pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss port e
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 275 13.1.1 features features of the spi module include: master or slave mode operation full-duplex or single-wire bidirectional option programmable transmit bit rate double-buffered transmit and receive serial clock phase and polarity options slave select output selectable msb-?st or lsb-?st shifting 13.1.2 block diagrams this section includes block diagrams showing spi system connections, the internal organization of the spi module, and the spi clock dividers that control the master mode bit rate. 13.1.2.1 spi system block diagram figure 13-2 shows the spi modules of two mcus connected in a master-slave arrangement. the master device initiates all spi data transfers. during a transfer, the master shifts data out (on the mosi pin) to the slave while simultaneously shifting data in (on the miso pin) from the slave. the transfer effectively exchanges the data that was in the spi shift registers of the two spi systems. the spsck signal is a clock output from the master and an input to the slave. the slave device must be selected by a low level on the slave select input ( ss pin). in this system, the master device has con?ured its ss pin as an optional slave select output. figure 13-2. spi system connections 7 6 5 4 3 2 1 0 spi shifter clock generator 7 6 5 4 3 2 1 0 spi shifter ss spsck miso mosi ss spsck miso mosi master slave
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 276 freescale semiconductor the most common uses of the spi system include connecting simple shift registers for adding input or output ports or connecting small peripheral devices such as serial a/d or d/a converters. although figure 13-2 shows a system where data is exchanged between two mcus, many practical systems involve simpler connections where data is unidirectionally transferred from the master mcu to a slave or from a slave to the master mcu. 13.1.2.2 spi module block diagram figure 13-3 is a block diagram of the spi module. the central element of the spi is the spi shift register. data is written to the double-buffered transmitter (write to spid) and gets transferred to the spi shift register at the start of a data transfer. after shifting in a byte of data, the data is transferred into the double-buffered receiver where it can be read (read from spid). pin multiplexing logic controls connections between mcu pins and the spi module. when the spi is con?ured as a master, the clock output is routed to the spsck pin, the shifter output is routed to mosi, and the shifter input is routed from the miso pin. when the spi is con?ured as a slave, the spsck pin is routed to the clock input of the spi, the shifter output is routed to miso, and the shifter input is routed from the mosi pin. in the external spi system, simply connect all spsck pins to each other, all miso pins together, and all mosi pins together. peripheral devices often use slightly different names for these pins.
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 277 figure 13-3. spi module block diagram 13.1.3 spi baud rate generation as shown in figure 13-4 , the clock source for the spi baud rate generator is the bus clock. the three prescale bits (sppr2:sppr1:sppr0) choose a prescale divisor of 1, 2, 3, 4, 5, 6, 7, or 8. the three rate select bits (spr2:spr1:spr0) divide the output of the prescaler stage by 2, 4, 8, 16, 32, 64, 128, or 256 to get the internal spi master mode bit-rate clock. spi shift register shift clock shift direction rx buffer full tx buffer empty shift out shift in enable spi system clock logic clock generator bus rate clock master/slave mode select mode fault detection master clock slave clock spi interrupt request pin control m s master/ slave mosi (momi) miso (siso) spsck ss m s s m modf spe lsbfe mstr sprf sptef sptie spie modfen ssoe spc0 bidiroe spibr tx buffer (write spid) rx buffer (read spid)
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 278 freescale semiconductor figure 13-4. spi baud rate generation 13.2 external signal description the spi optionally shares four port pins. the function of these pins depends on the settings of spi control bits. when the spi is disabled (spe = 0), these four pins revert to being general-purpose port i/o pins that are not controlled by the spi. 13.2.1 spsck ?spi serial clock when the spi is enabled as a slave, this pin is the serial clock input. when the spi is enabled as a master, this pin is the serial clock output. 13.2.2 mosi ?master data out, slave data in when the spi is enabled as a master and spi pin control zero (spc0) is 0 (not bidirectional mode), this pin is the serial data output. when the spi is enabled as a slave and spc0 = 0, this pin is the serial data input. if spc0 = 1 to select single-wire bidirectional mode, and master mode is selected, this pin becomes the bidirectional data i/o pin (momi). also, the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and slave mode is selected, this pin is not used by the spi and reverts to being a general-purpose port i/o pin. 13.2.3 miso ?master data in, slave data out when the spi is enabled as a master and spi pin control zero (spc0) is 0 (not bidirectional mode), this pin is the serial data input. when the spi is enabled as a slave and spc0 = 0, this pin is the serial data output. if spc0 = 1 to select single-wire bidirectional mode, and slave mode is selected, this pin becomes the bidirectional data i/o pin (siso) and the bidirectional mode output enable bit determines whether the pin acts as an input (bidiroe = 0) or an output (bidiroe = 1). if spc0 = 1 and master mode is selected, this pin is not used by the spi and reverts to being a general-purpose port i/o pin. 13.2.4 ss ?slave select when the spi is enabled as a slave, this pin is the low-true slave select input. when the spi is enabled as a master and mode fault enable is off (modfen = 0), this pin is not used by the spi and reverts to being a general-purpose port i/o pin. when the spi is enabled as a master and modfen = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (ssoe = 0) or as the slave select output (ssoe = 1). divide by 2, 4, 8, 16, 32, 64, 128, or 256 divide by 1, 2, 3, 4, 5, 6, 7, or 8 prescaler clock rate divider sppr2:sppr1:sppr0 spr2:spr1:spr0 bus clock master spi bit rate
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 279 13.3 modes of operation 13.3.1 spi in stop modes the spi is disabled in all stop modes, regardless of the settings before executing the stop instruction. during either stop1 or stop2 mode, the spi module will be fully powered down. upon wake-up from stop1 or stop2 mode, the spi module will be in the reset state. during stop3 mode, clocks to the spi module are halted. no registers are affected. if stop3 is exited with a reset, the spi will be put into its reset state. if stop3 is exited with an interrupt, the spi continues from the state it was in when stop3 was entered. 13.4 register de?ition the spi has ve 8-bit registers to select spi options, control baud rate, report spi status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all spi registers. this section refers to registers and control bits only by their names, and a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 13.4.1 spi control register 1 (spic1) this read/write register includes the spi enable control, interrupt enables, and con?uration options. 76543210 r spie spe sptie mstr cpol cpha ssoe lsbfe w reset 00000100 figure 13-5. spi control register 1 (spic1) table 13-1. spic1 field descriptions field description 7 spie spi interrupt enable (for sprf and modf) ?this is the interrupt enable for spi receive buffer full (sprf) and mode fault (modf) events. 0 interrupts from sprf and modf inhibited (use polling) 1 when sprf or modf is 1, request a hardware interrupt 6 spe spi system enable disabling the spi halts any transfer that is in progress, clears data buffers, and initializes internal state machines. sprf is cleared and sptef is set to indicate the spi transmit data buffer is empty. 0 spi system inactive 1 spi system enabled 5 sptie spi transmit interrupt enable ?this is the interrupt enable bit for spi transmit buffer empty (sptef). 0 interrupts from sptef inhibited (use polling) 1 when sptef is 1, hardware interrupt requested
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 280 freescale semiconductor note ensure that the spi should not be disabled (spe=0) at the same time as a bit change to the cpha bit. these changes should be performed as separate operations or unexpected behavior may occur. 13.4.2 spi control register 2 (spic2) this read/write register is used to control optional features of the spi system. bits 7, 6, 5, and 2 are not implemented and always read 0. 4 mstr master/slave mode select 0 spi module con?ured as a slave spi device 1 spi module con?ured as a master spi device 3 cpol clock polarity this bit effectively places an inverter in series with the clock signal from a master spi or to a slave spi device. refer to section 13.5.1, ?pi clock formats for more details. 0 active-high spi clock (idles low) 1 active-low spi clock (idles high) 2 cpha clock phase ?this bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. refer to section 13.5.1, ?pi clock formats for more details. 0 first edge on spsck occurs at the middle of the ?st cycle of an 8-cycle data transfer 1 first edge on spsck occurs at the start of the ?st cycle of an 8-cycle data transfer 1 ssoe slave select output enable ?this bit is used in combination with the mode fault enable (modfen) bit in spcr2 and the master/slave (mstr) control bit to determine the function of the ss pin as shown in table 13-2 . 0 lsbfe lsb first (shifter direction) 0 spi serial data transfers start with most signi?ant bit 1 spi serial data transfers start with least signi?ant bit table 13-2. ss pin function modfen ssoe master mode slave mode 0 0 general-purpose i/o (not spi) slave select input 0 1 general-purpose i/o (not spi) slave select input 10 ss input for mode fault slave select input 1 1 automatic ss output slave select input 76543210 r000 modfen bidiroe 0 spiswai spc0 w reset 00000000 = unimplemented or reserved figure 13-6. spi control register 2 (spic2) table 13-1. spic1 field descriptions (continued) field description
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 281 13.4.3 spi baud rate register (spibr) this register is used to set the prescaler and bit rate divisor for an spi master. this register may be read or written at any time. table 13-3. spic2 register field descriptions field description 4 modfen master mode-fault function enable when the spi is con?ured for slave mode, this bit has no meaning or effect. (the ss pin is the slave select input.) in master mode, this bit determines how the ss pin is used (refer to table 13-2 for more details). 0 mode fault function disabled, master ss pin reverts to general-purpose i/o not controlled by spi 1 mode fault function enabled, master ss pin acts as the mode fault input or the slave select output 3 bidiroe bidirectional mode output enable ?when bidirectional mode is enabled by spi pin control 0 (spc0) = 1, bidiroe determines whether the spi data output driver is enabled to the single bidirectional spi i/o pin. depending on whether the spi is con?ured as a master or a slave, it uses either the mosi (momi) or miso (siso) pin, respectively, as the single spi data i/o pin. when spc0 = 0, bidiroe has no meaning or effect. 0 output driver disabled so spi data i/o pin acts as an input 1 spi i/o pin enabled as an output 1 spiswai spi stop in wait mode 0 spi clocks continue to operate in wait mode 1 spi clocks stop when the mcu enters wait mode 0 spc0 spi pin control 0 the spc0 bit chooses single-wire bidirectional mode. if mstr = 0 (slave mode), the spi uses the miso (siso) pin for bidirectional spi data transfers. if mstr = 1 (master mode), the spi uses the mosi (momi) pin for bidirectional spi data transfers. when spc0 = 1, bidiroe is used to enable or disable the output driver for the single bidirectional spi i/o pin. 0 spi uses separate pins for data input and data output 1 spi con?ured for single-wire bidirectional operation 76543210 r0 sppr2 sppr1 sppr0 0 spr2 spr1 spr0 w reset 00000000 = unimplemented or reserved figure 13-7. spi baud rate register (spibr) table 13-4. spibr register field descriptions field description 6:4 sppr[2:0] spi baud rate prescale divisor this 3-bit ?ld selects one of eight divisors for the spi baud rate prescaler as shown in table 13-5 . the input to this prescaler is the bus rate clock (busclk). the output of this prescaler drives the input of the spi baud rate divider (see figure 13-4 ). 2:0 spr[2:0] spi baud rate divisor this 3-bit ?ld selects one of eight divisors for the spi baud rate divider as shown in table 13-6 . the input to this divider comes from the spi baud rate prescaler (see figure 13-4 ). the output of this divider is the spi bit rate clock for master mode.
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 282 freescale semiconductor 13.4.4 spi status register (spis) this register has three read-only status bits. bits 6, 3, 2, 1, and 0 are not implemented and always read 0. writes have no meaning or effect. table 13-5. spi baud rate prescaler divisor sppr2:sppr1:sppr0 prescaler divisor 0:0:0 1 0:0:1 2 0:1:0 3 0:1:1 4 1:0:0 5 1:0:1 6 1:1:0 7 1:1:1 8 table 13-6. spi baud rate divisor spr2:spr1:spr0 rate divisor 0:0:0 2 0:0:1 4 0:1:0 8 0:1:1 16 1:0:0 32 1:0:1 64 1:1:0 128 1:1:1 256 76543210 r sprf 0 sptef modf 0000 w reset 00100000 = unimplemented or reserved figure 13-8. spi status register (spis)
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 283 13.4.5 spi data register (spid) reads of this register return the data read from the receive data buffer. writes to this register write data to the transmit data buffer. when the spi is con?ured as a master, writing data to the transmit data buffer initiates an spi transfer. data should not be written to the transmit data buffer unless the spi transmit buffer empty ?g (sptef) is set, indicating there is room in the transmit buffer to queue a new transmit byte. data may be read from spid any time after sprf is set and before another transfer is ?ished. failure to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition and the data from the new transfer is lost. table 13-7. spis register field descriptions field description 7 sprf spi read buffer full flag sprf is set at the completion of an spi transfer to indicate that received data may be read from the spi data register (spid). sprf is cleared by reading sprf while it is set, then reading the spi data register. 0 no data available in the receive data buffer 1 data available in the receive data buffer 5 sptef spi transmit buffer empty flag this bit is set when there is room in the transmit data buffer. it is cleared by reading spis with sptef set, followed by writing a data value to the transmit buffer at spid. spis must be read with sptef = 1 before writing data to spid or the spid write will be ignored. sptef generates an sptef cpu interrupt request if the sptie bit in the spic1 is also set. sptef is automatically set when a data byte transfers from the transmit buffer into the transmit shift register. for an idle spi (no data in the transmit buffer or the shift register and no transfer in progress), data written to spid is transferred to the shifter almost immediately so sptef is set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. after completion of the transfer of the value in the shift register, the queued value from the transmit buffer will automatically move to the shifter and sptef will be set to indicate there is room for new data in the transmit buffer. if no new data is waiting in the transmit buffer, sptef simply remains set and no data moves from the buffer to the shifter. 0 spi transmit buffer not empty 1 spi transmit buffer empty 4 modf master mode fault flag ?modf is set if the spi is con?ured as a master and the slave select input goes low, indicating some other spi device is also con?ured as a master. the ss pin acts as a mode fault error input only when mstr = 1, modfen = 1, and ssoe = 0; otherwise, modf will never be set. modf is cleared by reading modf while it is 1, then writing to spi control register 1 (spic1). 0 no mode fault error 1 mode fault error detected 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 13-9. spi data register (spid)
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 284 freescale semiconductor 13.5 functional description an spi transfer is initiated by checking for the spi transmit buffer empty ?g (sptef = 1) and then writing a byte of data to the spi data register (spid) in the master spi device. when the spi shift register is available, this byte of data is moved from the transmit data buffer to the shifter, sptef is set to indicate there is room in the buffer to queue another transmit character if desired, and the spi serial transfer starts. during the spi transfer, data is sampled (read) on the miso pin at one spsck edge and shifted, changing the bit value on the mosi pin, one-half spsck cycle later. after eight spsck cycles, the data that was in the shift register of the master has been shifted out the mosi pin to the slave while eight bits of data were shifted in the miso pin into the masters shift register. at the end of this transfer, the received data byte is moved from the shifter into the receive data buffer and sprf is set to indicate the data can be read by reading spid. if another byte of data is waiting in the transmit buffer at the end of a transfer, it is moved into the shifter, sptef is set, and a new transfer is started. normally, spi data is transferred most signi?ant bit (msb) ?st. if the least signi?ant bit ?st enable (lsbfe) bit is set, spi data is shifted lsb ?st. when the spi is con?ured as a slave, its ss pin must be driven low before a transfer starts and ss must stay low throughout the transfer. if a clock format where cpha = 0 is selected, ss must be driven to a logic 1 between successive transfers. if cpha = 1, ss may remain low between successive transfers. see section 13.5.1, ?pi clock formats ?for more details. because the transmitter and receiver are double buffered, a second byte, in addition to the byte currently being shifted out, can be queued into the transmit data buffer, and a previously received character can be in the receive data buffer while a new character is being shifted in. the sptef ?g indicates when the transmit buffer has room for a new character. the sprf ?g indicates when a received character is available in the receive data buffer. the received character must be read out of the receive buffer (read spid) before the next transfer is ?ished or a receive overrun error results. in the case of a receive overrun, the new data is lost because the receive buffer still held the previous character and was not ready to accept the new data. there is no indication for such an overrun condition so the application system designer must ensure that previous data has been read from the receive buffer before a new transfer is initiated. 13.5.1 spi clock formats to accommodate a wide variety of synchronous serial peripherals from different manufacturers, the spi system has a clock polarity (cpol) bit and a clock phase (cpha) control bit to select one of four clock formats for data transfers. cpol selectively inserts an inverter in series with the clock. cpha chooses between two different clock phase relationships between the clock and data. figure 13-10 shows the clock formats when cpha = 1. at the top of the ?ure, the eight bit times are shown for reference with bit 1 starting at the ?st spsck edge and bit 8 ending one-half spsck cycle after the sixteenth spsck edge. the msb ?st and lsb ?st lines show the order of spi data bits depending on the setting in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a speci? transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 285 pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low one-half spsck cycle before the start of the transfer and goes back high at the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 13-10. spi clock formats (cpha = 1) when cpha = 1, the slave begins to drive its miso output when ss goes to active low, but the data is not de?ed until the ?st spsck edge. the ?st spsck edge shifts the ?st bit of data from the shifter onto the mosi output of the master and the miso output of the slave. the next spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi inputs, respectively. at the third spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled, and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when chpa = 1, the slaves ss input is not required to go to its inactive high level between transfers. figure 13-11 shows the clock formats when cpha = 0. at the top of the ?ure, the eight bit times are shown for reference with bit 1 starting as the slave is selected ( ss in goes low), and bit 8 ends at the last spsck edge. the msb ?st and lsb ?st lines show the order of spi data bits depending on the setting bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 286 freescale semiconductor in lsbfe. both variations of spsck polarity are shown, but only one of these waveforms applies for a speci? transfer, depending on the value in cpol. the sample in waveform applies to the mosi input of a slave or the miso input of a master. the mosi waveform applies to the mosi output pin from a master and the miso waveform applies to the miso output from a slave. the ss out waveform applies to the slave select output from a master (provided modfen and ssoe = 1). the master ss output goes to active low at the start of the ?st bit time of the transfer and goes back high one-half spsck cycle after the end of the eighth bit time of the transfer. the ss in waveform applies to the slave select input of a slave. figure 13-11. spi clock formats (cpha = 0) when cpha = 0, the slave begins to drive its miso output with the ?st data bit value (msb or lsb depending on lsbfe) when ss goes to active low. the ?st spsck edge causes both the master and the slave to sample the data bit values on their miso and mosi inputs, respectively. at the second spsck edge, the spi shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the mosi and miso outputs of the master and slave, respectively. when cpha = 0, the slaves ss input must go to its inactive high level between transfers. bit time # (reference) msb first lsb first spsck (cpol = 0) spsck (cpol = 1) sample in (miso or mosi) mosi (master out) miso (slave out) ss out (master) ss in (slave) bit 7 bit 0 bit 6 bit 1 bit 2 bit 5 bit 1 bit 6 bit 0 bit 7 12 67 8 ... ... ...
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 287 13.5.2 spi interrupts there are three ?g bits, two interrupt mask bits, and one interrupt vector associated with the spi system. the spi interrupt enable mask (spie) enables interrupts from the spi receiver full ?g (sprf) and mode fault ?g (modf). the spi transmit interrupt enable mask (sptie) enables interrupts from the spi transmit buffer empty ?g (sptef). when one of the ?g bits is set, and the associated interrupt mask bit is set, a hardware interrupt request is sent to the cpu. if the interrupt mask bits are cleared, software can poll the associated ?g bits instead of using interrupts. the spi interrupt service routine (isr) should check the ?g bits to determine what event caused the interrupt. the service routine should also clear the ?g bit(s) before returning from the isr (usually near the beginning of the isr). 13.5.3 mode fault detection a mode fault occurs and the mode fault ?g (modf) becomes set when a master spi device detects an error on the ss pin (provided the ss pin is con?ured as the mode fault input signal). the ss pin is con?ured to be the mode fault input signal when mstr = 1, mode fault enable is set (modfen = 1), and slave select output enable is clear (ssoe = 0). the mode fault detection feature can be used in a system where more than one spi device might become a master at the same time. the error is detected when a masters ss pin is low, indicating that some other spi device is trying to address this master as if it were a slave. this could indicate a harmful output driver con?ct, so the mode fault logic is designed to disable all spi output drivers when such an error is detected. when a mode fault is detected, modf is set and mstr is cleared to change the spi con?uration back to slave mode. the output drivers on the spsck, mosi, and miso (if not bidirectional mode) are disabled. modf is cleared by reading it while it is set, then writing to the spi control register 1 (spic1). user software should verify the error condition has been corrected before changing the spi back to master mode.
chapter 13 serial peripheral interface (s08spiv3) mc9s08de60 series data sheet, rev. 3 288 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 289 chapter 14 serial communications interface (s08sciv4) 14.1 introduction all mcus in the mc9s08de60 series include sci1 and sci2. note mc9s08de60 series devices operate at a higher voltage range (2.7 v to 5.5 v) and do not include stop1 mode. please ignore references to stop1. the rxd1 pin does not contain a clamp diode to v dd and should not be driven above v dd . the voltage measured on the internally pulled up rxd1 pin may be as low as v dd ?0.7 v. the internal gates connected to this pin are pulled all the way to v dd . 14.1.1 sci2 con?uration information the sci2 module pins, txd2 and rxd2 can be repositioned under software control using sci2ps in sopt1 as shown in table 14-1 . sci2ps in sopt1 selects which general-purpose i/o ports are associated with sci2 operation. table 14-1. sci2 position options sci2ps in sopt1 port pin for txd2 port pin for rxd2 0 (default) ptf0 ptf1 1 pte6 pte7
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 290 freescale semiconductor figure 14-1. mc9s08de60/32 block diagram emphasizing the sci blocks and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 291 14.1.2 features features of sci module include: full-duplex, standard non-return-to-zero (nrz) format double-buffered transmitter and receiver with separate enables programmable baud rates (13-bit modulo divider) interrupt-driven or polled operation: transmit data register empty and transmission complete receive data register full receive overrun, parity error, framing error, and noise error idle receiver detect active edge on receive pin break detect supporting lin hardware parity generation and checking programmable 8-bit or 9-bit character length receiver wakeup by idle-line or address-mark optional 13-bit break character generation / 11-bit break character detection selectable transmitter output polarity 14.1.3 modes of operation see section 14.3, ?unctional description ,?for details concerning sci operation in these modes: 8- and 9-bit data modes stop mode operation loop mode single-wire mode
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 292 freescale semiconductor 14.1.4 block diagram figure 14-2 shows the transmitter portion of the sci. figure 14-2. sci transmitter block diagram h 8 7 6 5 4 3 2 1 0 l scid ?tx buffer (write-only) internal bus stop 11-bit transmit shift register start shift direction lsb 1 baud rate clock parity generation transmit control shift enable preamble (all 1s) break (all 0s) sci controls txd txd direction to txd pin logic loop control to receive data in to txd pin tx interrupt request loops rsrc tie tc tdre m pt pe tcie te sbk t8 txdir load from scixd txinv brk13
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 293 figure 14-3 shows the receiver portion of the sci. figure 14-3. sci receiver block diagram h 8 7 6 5 4 3 2 1 0 l scid ?rx buffer (read-only) internal bus stop 11-bit receive shift register start shift direction lsb from rxd pin rate clock rx interrupt request data recovery divide 16 baud single-wire loop control wakeup logic all 1s msb from transmitter error interrupt request parity checking by 16 rdrf rie idle ilie or orie fe feie nf neie pf loops peie pt pe rsrc wake ilt rwu m lbkdif lbkdie rxedgif rxedgie active edge detect rxinv lbkde rwuid
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 294 freescale semiconductor 14.2 register de?ition the sci has eight 8-bit registers to control baud rate, select sci options, report sci status, and for transmit/receive data. refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all sci registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 14.2.1 sci baud rate registers (scixbdh, scixbdl) this pair of registers controls the prescale divisor for sci baud rate generation. to update the 13-bit baud rate setting [sbr12:sbr0], ?st write to scixbdh to buffer the high half of the new value and then write to scixbdl. the working value in scixbdh does not change until scixbdl is written. scixbdl is reset to a non-zero value, so after reset the baud rate generator remains disabled until the ?st time the receiver or transmitter is enabled (re or te bits in scixc2 are written to 1). 76543210 r lbkdie rxedgie 0 sbr12 sbr11 sbr10 sbr9 sbr8 w reset 00000000 = unimplemented or reserved figure 14-4. sci baud rate register (scixbdh) table 14-2. scixbdh field descriptions field description 7 lbkdie lin break detect interrupt enable (for lbkdif) 0 hardware interrupts from lbkdif disabled (use polling). 1 hardware interrupt requested when lbkdif ?g is 1. 6 rxedgie rxd input active edge interrupt enable (for rxedgif) 0 hardware interrupts from rxedgif disabled (use polling). 1 hardware interrupt requested when rxedgif ?g is 1. 4:0 sbr[12:8] baud rate modulo divisor ?the 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in table 14-3 .
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 295 14.2.2 sci control register 1 (scixc1) this read/write register is used to control various optional features of the sci system. 76543210 r sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 w reset 00000100 figure 14-5. sci baud rate register (scixbdl) table 14-3. scixbdl field descriptions field description 7:0 sbr[7:0] baud rate modulo divisor ?these 13 bits in sbr[12:0] are referred to collectively as br, and they set the modulo divide rate for the sci baud rate generator. when br = 0, the sci baud rate generator is disabled to reduce supply current. when br = 1 to 8191, the sci baud rate = busclk/(16 br). see also br bits in table 14-2 . 76543210 r loops sciswai rsrc m wake ilt pe pt w reset 00000000 figure 14-6. sci control register 1 (scixc1) table 14-4. scixc1 field descriptions field description 7 loops loop mode select ?selects between loop back modes and normal 2-pin full-duplex modes. when loops = 1, the transmitter output is internally connected to the receiver input. 0 normal operation ?rxd and txd use separate pins. 1 loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (see rsrc bit.) rxd pin is not used by sci. 6 sciswai sci stops in wait mode 0 sci clocks continue to run in wait mode so the sci can be the source of an interrupt that wakes up the cpu. 1 sci clocks freeze while cpu is in wait mode. 5 rsrc receiver source select ?this bit has no meaning or effect unless the loops bit is set to 1. when loops = 1, the receiver input is internally connected to the txd pin and rsrc determines whether this connection is also connected to the transmitter output. 0 provided loops = 1, rsrc = 0 selects internal loop back mode and the sci does not use the rxd pins. 1 single-wire sci mode where the txd pin is connected to the transmitter output and receiver input. 4 m 9-bit or 8-bit mode select 0 normal ?start + 8 data bits (lsb ?st) + stop. 1 receiver and transmitter use 9-bit data characters start + 8 data bits (lsb ?st) + 9th data bit + stop.
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 296 freescale semiconductor 14.2.3 sci control register 2 (scixc2) this register can be read or written at any time. 3 wake receiver wakeup method select ?refer to section 14.3.3.2, ?eceiver wakeup operation ?for more information. 0 idle-line wakeup. 1 address-mark wakeup. 2 ilt idle line type select ?setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. refer to section 14.3.3.2.1, ?dle-line wakeup ?for more information. 0 idle character bit count starts after start bit. 1 idle character bit count starts after stop bit. 1 pe parity enable enables hardware parity generation and checking. when parity is enabled, the most signi?ant bit (msb) of the data character (eighth or ninth data bit) is treated as the parity bit. 0 no hardware parity generation or checking. 1 parity enabled. 0 pt parity type provided parity is enabled (pe = 1), this bit selects even or odd parity. odd parity means the total number of 1s in the data character, including the parity bit, is odd. even parity means the total number of 1s in the data character, including the parity bit, is even. 0 even parity. 1 odd parity. 76543210 r tie tcie rie ilie te re rwu sbk w reset 00000000 figure 14-7. sci control register 2 (scixc2) table 14-5. scixc2 field descriptions field description 7 tie transmit interrupt enable (for tdre) 0 hardware interrupts from tdre disabled (use polling). 1 hardware interrupt requested when tdre ?g is 1. 6 tcie transmission complete interrupt enable (for tc) 0 hardware interrupts from tc disabled (use polling). 1 hardware interrupt requested when tc ?g is 1. 5 rie receiver interrupt enable (for rdrf) 0 hardware interrupts from rdrf disabled (use polling). 1 hardware interrupt requested when rdrf ?g is 1. 4 ilie idle line interrupt enable (for idle) 0 hardware interrupts from idle disabled (use polling). 1 hardware interrupt requested when idle ?g is 1. table 14-4. scixc1 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 297 14.2.4 sci status register 1 (scixs1) this register has eight read-only status ?gs. writes have no effect. special software sequences (which do not involve writing to this register) are used to clear these status ?gs. 3 te transmitter enable 0 transmitter off. 1 transmitter on. te must be 1 in order to use the sci transmitter. when te = 1, the sci forces the txd pin to act as an output for the sci system. when the sci is con?ured for single-wire operation (loops = rsrc = 1), txdir controls the direction of traf? on the single sci communication line (txd pin). te also can be used to queue an idle character by writing te = 0 then te = 1 while a transmission is in progress. refer to section 14.3.2.1, ?end break and queued idle ?for more details. when te is written to 0, the transmitter keeps control of the port txd pin until any data, queued idle, or queued break character ?ishes transmitting before allowing the pin to revert to a general-purpose i/o pin. 2 re receiver enable ?when the sci receiver is off, the rxd pin reverts to being a general-purpose port i/o pin. if loops = 1 the rxd pin reverts to being a general-purpose i/o pin even if re = 1. 0 receiver off. 1 receiver on. 1 rwu receiver wakeup control ?this bit can be written to 1 to place the sci receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. the wakeup condition is either an idle line between messages (wake = 0, idle-line wakeup), or a logic 1 in the most signi?ant data bit in a character (wake = 1, address-mark wakeup). application software sets rwu and (normally) a selected hardware condition automatically clears rwu. refer to section 14.3.3.2, ?eceiver wakeup operation ?for more details. 0 normal sci receiver operation. 1 sci receiver in standby waiting for wakeup condition. 0 sbk send break writing a 1 and then a 0 to sbk queues a break character in the transmit data stream. additional break characters of 10 or 11 (13 or 14 if brk13 = 1) bit times of logic 0 are queued as long as sbk = 1. depending on the timing of the set and clear of sbk relative to the information currently being transmitted, a second break character may be queued before software clears sbk. refer to section 14.3.2.1, ?end break and queued idle ?for more details. 0 normal transmitter operation. 1 queue break character(s) to be sent. 76543210 r tdre tc rdrf idle or nf fe pf w reset 11000000 = unimplemented or reserved figure 14-8. sci status register 1 (scixs1) table 14-5. scixc2 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 298 freescale semiconductor table 14-6. scixs1 field descriptions field description 7 tdre transmit data register empty flag tdre is set out of reset and when a transmit data value transfers from the transmit data buffer to the transmit shifter, leaving room for a new character in the buffer. to clear tdre, read scixs1 with tdre = 1 and then write to the sci data register (scixd). 0 transmit data register (buffer) full. 1 transmit data register (buffer) empty. 6 tc transmission complete flag ?tc is set out of reset and when tdre = 1 and no data, preamble, or break character is being transmitted. 0 transmitter active (sending data, a preamble, or a break). 1 transmitter idle (transmission activity complete). tc is cleared automatically by reading scixs1 with tc = 1 and then doing one of the following three things: write to the sci data register (scixd) to transmit new data queue a preamble by changing te from 0 to 1 queue a break character by writing 1 to sbk in scixc2 5 rdrf receive data register full flag rdrf becomes set when a character transfers from the receive shifter into the receive data register (scixd). to clear rdrf, read scixs1 with rdrf = 1 and then read the sci data register (scixd). 0 receive data register empty. 1 receive data register full. 4 idle idle line flag ?idle is set when the sci receive line becomes idle for a full character time after a period of activity. when ilt = 0, the receiver starts counting idle bit times after the start bit. so if the receive character is all 1s, these bit times and the stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the m control bit) needed for the receiver to detect an idle line. when ilt = 1, the receiver doesn? start counting idle bit times until after the stop bit. so the stop bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high needed for the receiver to detect an idle line. to clear idle, read scixs1 with idle = 1 and then read the sci data register (scixd). after idle has been cleared, it cannot become set again until after a new character has been received and rdrf has been set. idle will get set only once even if the receive line remains idle for an extended period. 0 no idle line detected. 1 idle line was detected. 3 or receiver overrun flag or is set when a new serial character is ready to be transferred to the receive data register (buffer), but the previously received character has not been read from scixd yet. in this case, the new character (and all associated error information) is lost because there is no room to move it into scixd. to clear or, read scixs1 with or = 1 and then read the sci data register (scixd). 0 no overrun. 1 receive overrun (new sci data lost). 2 nf noise flag the advanced sampling technique used in the receiver takes seven samples during the start bit and three samples in each data bit and the stop bit. if any of these samples disagrees with the rest of the samples within any bit time in the frame, the ?g nf will be set at the same time as the ?g rdrf gets set for the character. to clear nf, read scixs1 and then read the sci data register (scixd). 0 no noise detected. 1 noise detected in the received character in scixd.
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 299 14.2.5 sci status register 2 (scixs2) this register has one read-only status ?g. 1 fe framing error flag fe is set at the same time as rdrf when the receiver detects a logic 0 where the stop bit was expected. this suggests the receiver was not properly aligned to a character frame. to clear fe, read scixs1 with fe = 1 and then read the sci data register (scixd). 0 no framing error detected. this does not guarantee the framing is correct. 1 framing error. 0 pf parity error flag ?pf is set at the same time as rdrf when parity is enabled (pe = 1) and the parity bit in the received character does not agree with the expected parity value. to clear pf, read scixs1 and then read the sci data register (scixd). 0 no parity error. 1 parity error. 76543210 r lbkdif rxedgif 0 rxinv rwuid brk13 lbkde raf w reset 00000000 = unimplemented or reserved figure 14-9. sci status register 2 (scixs2) table 14-7. scixs2 field descriptions field description 7 lbkdif lin break detect interrupt flag lbkdif is set when the lin break detect circuitry is enabled and a lin break character is detected. lbkdif is cleared by writing a ??to it. 0 no lin break character has been detected. 1 lin break character has been detected. 6 rxedgif rxd pin active edge interrupt flag ?rxedgif is set when an active edge (falling if rxinv = 0, rising if rxinv=1) on the rxd pin occurs. rxedgif is cleared by writing a ??to it. 0 no active edge on the receive pin has occurred. 1 an active edge on the receive pin has occurred. 4 rxinv 1 receive data inversion ?setting this bit reverses the polarity of the received data input. 0 receive data not inverted 1 receive data inverted 3 rwuid receive wake up idle detect rwuid controls whether the idle character that wakes up the receiver sets the idle bit. 0 during receive standby state (rwu = 1), the idle bit does not get set upon detection of an idle character. 1 during receive standby state (rwu = 1), the idle bit gets set upon detection of an idle character. 2 brk13 break character generation length brk13 is used to select a longer transmitted break character length. detection of a framing error is not affected by the state of this bit. 0 break character is transmitted with length of 10 bit times (11 if m = 1) 1 break character is transmitted with length of 13 bit times (14 if m = 1) table 14-6. scixs1 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 300 freescale semiconductor when using an internal oscillator in a lin system, it is necessary to raise the break detection threshold by one bit time. under the worst case timing conditions allowed in lin, it is possible that a 0x00 data character can appear to be 10.26 bit times long at a slave which is running 14% faster than the master. this would trigger normal break detection circuitry which is designed to detect a 10 bit break symbol. when the lbkde bit is set, framing errors are inhibited and the break detection threshold changes from 10 bits to 11 bits, preventing false detection of a 0x00 data character as a lin break symbol. 14.2.6 sci control register 3 (scixc3) 1 lbkde lin break detection enable ?lbkde is used to select a longer break character detection length. while lbkde is set, framing error (fe) and receive data register full (rdrf) ?gs are prevented from setting. 0 break character is detected at length of 10 bit times (11 if m = 1). 1 break character is detected at length of 11 bit times (12 if m = 1). 0 raf receiver active flag raf is set when the sci receiver detects the beginning of a valid start bit, and raf is cleared automatically when the receiver detects an idle line. this status ?g can be used to check whether an sci character is being received before instructing the mcu to go to stop mode. 0 sci receiver idle waiting for a start bit. 1 sci receiver active (rxd input not idle). 1 setting rxinv inverts the rxd input for all cases: data bits, start and stop bits, break, and idle. 76543210 rr8 t8 txdir txinv orie neie feie peie w reset 00000000 = unimplemented or reserved figure 14-10. sci control register 3 (scixc3) table 14-8. scixc3 field descriptions field description 7 r8 ninth data bit for receiver ?when the sci is con?ured for 9-bit data (m = 1), r8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the scixd register. when reading 9-bit data, read r8 before reading scixd because reading scixd completes automatic ?g clearing sequences which could allow r8 and scixd to be overwritten with new data. 6 t8 ninth data bit for transmitter when the sci is con?ured for 9-bit data (m = 1), t8 may be thought of as a ninth transmit data bit to the left of the msb of the data in the scixd register. when writing 9-bit data, the entire 9-bit value is transferred to the sci shift register after scixd is written so t8 should be written (if it needs to change from its previous value) before scixd is written. if t8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need not be written each time scixd is written. 5 txdir txd pin direction in single-wire mode ?when the sci is con?ured for single-wire half-duplex operation (loops = rsrc = 1), this bit determines the direction of data at the txd pin. 0 txd pin is an input in single-wire mode. 1 txd pin is an output in single-wire mode. table 14-7. scixs2 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 301 14.2.7 sci data register (scixd) this register is actually two separate registers. reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. reads and writes of this register are also involved in the automatic ?g clearing mechanisms for the sci status ?gs. 14.3 functional description the sci allows full-duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus. the sci comprises a baud rate generator, transmitter, and receiver block. the transmitter and receiver operate independently, although they use the same baud rate generator. during normal operation, the mcu monitors the status of the sci, writes the data to be transmitted, and processes received data. the following describes each of the blocks of the sci. 14.3.1 baud rate generation as shown in figure 14-12 , the clock source for the sci baud rate generator is the bus-rate clock. 4 txinv 1 transmit data inversion ?setting this bit reverses the polarity of the transmitted data output. 0 transmit data not inverted 1 transmit data inverted 3 orie overrun interrupt enable ?this bit enables the overrun ?g (or) to generate hardware interrupt requests. 0 or interrupts disabled (use polling). 1 hardware interrupt requested when or = 1. 2 neie noise error interrupt enable ?this bit enables the noise ?g (nf) to generate hardware interrupt requests. 0 nf interrupts disabled (use polling). 1 hardware interrupt requested when nf = 1. 1 feie framing error interrupt enable ?this bit enables the framing error ?g (fe) to generate hardware interrupt requests. 0 fe interrupts disabled (use polling). 1 hardware interrupt requested when fe = 1. 0 peie parity error interrupt enable ?this bit enables the parity error ?g (pf) to generate hardware interrupt requests. 0 pf interrupts disabled (use polling). 1 hardware interrupt requested when pf = 1. 1 setting txinv inverts the txd output for all cases: data bits, start and stop bits, break, and idle. 76543210 rr 7r 6r 5r 4r 3r 2r 1r 0 wt 7t 6t 5t 4t 3t 2t 1t 0 reset 00000000 figure 14-11. sci data register (scixd) table 14-8. scixc3 field descriptions (continued) field description
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 302 freescale semiconductor figure 14-12. sci baud rate generation sci communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. the mcu resynchronizes to bit boundaries on every high-to-low transition, but in the worst case, there are no such transitions in the full 10- or 11-bit time character frame so any mismatch in baud rate is accumulated for the whole character time. for a freescale semiconductor sci system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about 4.5percent for 8-bit data format and about 4 percent for 9-bit data format. although baud rate modulo divider settings do not always produce baud rates that exactly match standard rates, it is normally possible to get within a few percent, which is acceptable for reliable communications. 14.3.2 transmitter functional description this section describes the overall block diagram for the sci transmitter, as well as specialized functions for sending break and idle characters. the transmitter block diagram is shown in figure 14-2 . the transmitter output (txd) idle state defaults to logic high (txinv = 0 following reset). the transmitter output is inverted by setting txinv = 1. the transmitter is enabled by setting the te bit in scixc2. this queues a preamble character that is one full character frame of the idle state. the transmitter then remains idle until data is available in the transmit data buffer. programs store data into the transmit data buffer by writing to the sci data register (scixd). the central element of the sci transmitter is the transmit shift register that is either 10 or 11 bits long depending on the setting in the m control bit. for the remainder of this section, we will assume m = 0, selecting the normal 8-bit data mode. in 8-bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. when the transmit shift register is available for a new sci character, the value waiting in the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the transmit data register empty (tdre) status ?g is set to indicate another character may be written to the transmit data buffer at scixd. if no new character is waiting in the transmit data buffer after a stop bit is shifted out the txd pin, the transmitter sets the transmit complete ?g and enters an idle mode, with txd high, waiting for more characters to transmit. sbr12:sbr0 divide by tx baud rate rx sampling clock (16 baud rate) baud rate generator off if [sbr12:sbr0] = 0 busclk baud rate = busclk [sbr12:sbr0] 16 16 modulo divide by (1 through 8191)
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 303 writing 0 to te does not immediately release the pin to be a general-purpose i/o pin. any transmit activity that is in progress must ?st be completed. this includes data characters in progress, queued idle characters, and queued break characters. 14.3.2.1 send break and queued idle the sbk control bit in scixc2 is used to send break characters which were originally used to gain the attention of old teletype receivers. break characters are a full character time of logic 0 (10 bit times including the start and stop bits). a longer break of 13 bit times can be enabled by setting brk13 = 1. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the sbk bit. this action queues a break character to be sent as soon as the shifter is available. if sbk is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. if the receiving device is another freescale semiconductor sci, the break characters will be received as 0s in all eight data bits and a framing error (fe = 1) occurs. when idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake up any sleeping receivers. normally, a program would wait for tdre to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the te bit. this action queues an idle character to be sent as soon as the shifter is available. as long as the character in the shifter does not ?ish while te = 0, the sci transmitter never actually releases control of the txd pin. if there is a possibility of the shifter ?ishing while te = 0, set the general-purpose i/o controls so the pin that is shared with txd is an output driving a logic 1. this ensures that the txd line will look like a normal idle line even if the sci loses control of the port pin between writing 0 and then 1 to te. the length of the break character is affected by the brk13 and m bits as shown below. 14.3.3 receiver functional description in this section, the receiver block diagram ( figure 14-3 ) is used as a guide for the overall receiver functional description. next, the data sampling technique used to reconstruct receiver data is described in more detail. finally, two variations of the receiver wakeup function are explained. the receiver input is inverted by setting rxinv = 1. the receiver is enabled by setting the re bit in scixc2. character frames consist of a start bit of logic 0, eight (or nine) data bits (lsb ?st), and a stop bit of logic 1. for information about 9-bit data mode, refer to section 14.3.5.1, ?- and 9-bit data modes . for the remainder of this discussion, we assume the sci is con?ured for normal 8-bit data mode. after receiving the stop bit into the receive shifter, and provided the receive data register is not already full, the data character is transferred to the receive data register and the receive data register full (rdrf) status table 14-9. break character length brk13 m break character length 0 0 10 bit times 0 1 11 bit times 1 0 13 bit times 1 1 14 bit times
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 304 freescale semiconductor ?g is set. if rdrf was already set indicating the receive data register (buffer) was already full, the overrun (or) status ?g is set and the new data is lost. because the sci receiver is double-buffered, the program has one full character time after rdrf is set before the data in the receive data buffer must be read to avoid a receiver overrun. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf ?g is cleared automatically by a 2-step sequence which is normally satis?d in the course of the users program that handles receive data. refer to section 14.3.4, ?nterrupts and status flags?for more details about ?g clearing. 14.3.3.1 data sampling technique the sci receiver uses a 16 baud rate clock for sampling. the receiver starts by taking logic level samples at 16 times the baud rate to search for a falling edge on the rxd serial data input pin. a falling edge is de?ed as a logic 0 sample after three consecutive logic 1 samples. the 16 baud rate clock is used to divide the bit time into 16 segments labeled rt1 through rt16. when a falling edge is located, three more samples are taken at rt3, rt5, and rt7 to make sure this was a real start bit and not merely noise. if at least two of these three samples are 0, the receiver assumes it is synchronized to a receive character. the receiver then samples each bit time, including the start and stop bits, at rt8, rt9, and rt10 to determine the logic level for that bit. the logic level is interpreted to be that of the majority of the samples taken during the bit time. in the case of the start bit, the bit is assumed to be 0 if at least two of the samples at rt3, rt5, and rt7 are 0 even if one or all of the samples taken at rt8, rt9, and rt10 are 1s. if any sample in any bit time (including the start and stop bits) in a character frame fails to agree with the logic level for that bit, the noise ?g (nf) will be set when the received character is transferred to the receive data buffer. the falling edge detection logic continuously looks for falling edges, and if an edge is detected, the sample clock is resynchronized to bit times. this improves the reliability of the receiver in the presence of noise or mismatched baud rates. it does not improve worst case analysis because some characters do not have any extra falling edges anywhere in the character frame. in the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is ?led with three logic 1 samples so that a new start bit can be detected almost immediately. in the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error ?g is cleared. the receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if fe is still set. 14.3.3.2 receiver wakeup operation receiver wakeup is a hardware mechanism that allows an sci receiver to ignore the characters in a message that is intended for a different sci receiver. in such a system, all receivers evaluate the ?st character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (rwu) control bit in scixc2. when rwu bit is set, the status ?gs associated with the receiver (with the exception of the idle bit, idle, when rwuid bit is set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 305 message characters. at the end of a message, or at the beginning of the next message, all receivers automatically force rwu to 0 so all receivers wake up in time to look at the ?st character(s) of the next message. 14.3.3.2.1 idle-line wakeup when wake = 0, the receiver is con?ured for idle-line wakeup. in this mode, rwu is cleared automatically when the receiver detects a full character time of the idle-line level. the m control bit selects 8-bit or 9-bit data mode that determines how many bit times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits). when rwu is one and rwuid is zero, the idle condition that wakes up the receiver does not set the idle ?g. the receiver wakes up and waits for the ?st data character of the next message which will set the rdrf ?g and generate an interrupt if enabled. when rwuid is one, any idle condition sets the idle ?g and generates an interrupt if enabled, regardless of whether rwu is zero or one. the idle-line type (ilt) control bit selects one of two ways to detect an idle line. when ilt = 0, the idle bit counter starts after the start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. when ilt = 1, the idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the previous message. 14.3.3.2.2 address-mark wakeup when wake = 1, the receiver is con?ured for address-mark wakeup. in this mode, rwu is cleared automatically when the receiver detects a logic 1 in the most signi?ant bit of a received character (eighth bit in m = 0 mode and ninth bit in m = 1 mode). address-mark wakeup allows messages to contain idle characters but requires that the msb be reserved for use in address frames. the logic 1 msb of an address frame clears the rwu bit before the stop bit is received and sets the rdrf ?g. in this case the character with the msb set is received even though the receiver was sleeping during most of this character time. 14.3.4 interrupts and status flags the sci system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the interrupt. one interrupt vector is associated with the transmitter for tdre and tc events. another interrupt vector is associated with the receiver for rdrf, idle, rxedgif and lbkdif events, and a third vector is used for or, nf, fe, and pf error conditions. each of these ten interrupt sources can be separately masked by local interrupt enable masks. the ?gs can still be polled by software when the local masks are cleared to disable generation of hardware interrupt requests. the sci transmitter has two status ?gs that optionally can generate hardware interrupt requests. transmit data register empty (tdre) indicates when there is room in the transmit data buffer to write another transmit character to scixd. if the transmit interrupt enable (tie) bit is set, a hardware interrupt will be requested whenever tdre = 1. transmit complete (tc) indicates that the transmitter is ?ished transmitting all data, preamble, and break characters and is idle with txd at the inactive level. this ?g is often used in systems with modems to determine when it is safe to turn off the modem. if the transmit complete interrupt enable (tcie) bit is set, a hardware interrupt will be requested whenever tc = 1.
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 306 freescale semiconductor instead of hardware interrupts, software polling may be used to monitor the tdre and tc status ?gs if the corresponding tie or tcie local interrupt masks are 0s. when a program detects that the receive data register is full (rdrf = 1), it gets the data from the receive data register by reading scixd. the rdrf ?g is cleared by reading scixs1 while rdrf = 1 and then reading scixd. when polling is used, this sequence is naturally satis?d in the normal course of the user program. if hardware interrupts are used, scixs1 must be read in the interrupt service routine (isr). normally, this is done in the isr anyway to check for receive errors, so the sequence is automatically satis?d. the idle status ?g includes logic that prevents it from getting set repeatedly when the rxd line remains idle for an extended period of time. idle is cleared by reading scixs1 while idle = 1 and then reading scixd. after idle has been cleared, it cannot become set again until the receiver has received at least one new character and has set rdrf. if the associated error was detected in the received character that caused rdrf to be set, the error ?gs noise ?g (nf), framing error (fe), and parity error ?g (pf) get set at the same time as rdrf. these ?gs are not set in overrun cases. if rdrf was already set when a new character is ready to be transferred from the receive shifter to the receive data buffer, the overrun (or) ?g gets set instead the data along with any associated nf, fe, or pf condition is lost. at any time, an active edge on the rxd serial data input pin causes the rxedgif flag to set. the rxedgif ?g is cleared by writing a ? to it. this function does depend on the receiver being enabled (re = 1). 14.3.5 additional sci functions the following sections describe additional sci functions. 14.3.5.1 8- and 9-bit data modes the sci system (transmitter and receiver) can be con?ured to operate in 9-bit data mode by setting the m control bit in scixc1. in 9-bit mode, there is a ninth data bit to the left of the msb of the sci data register. for the transmit data buffer, this bit is stored in t8 in scixc3. for the receiver, the ninth bit is held in r8 in scixc3. for coherent writes to the transmit data buffer, write to the t8 bit before writing to scixd. if the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary to write to t8 again. when data is transferred from the transmit data buffer to the transmit shifter, the value in t8 is copied at the same time data is transferred from scixd to the shifter. 9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. in custom protocols, the ninth bit can also serve as a software-controlled marker.
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 307 14.3.5.2 stop mode operation during all stop modes, clocks to the sci module are halted. in stop1 and stop2 modes, all sci register data is lost and must be re-initialized upon recovery from these two stop modes. no sci module registers are affected in stop3 mode. the receive input active edge detect circuit is still active in stop3 mode, but not in stop2.. an active edge on the receive input brings the cpu out of stop3 mode if the interrupt is not masked (rxedgie = 1). note, because the clocks are halted, the sci module will resume operation upon exit from stop (only in stop3 mode). software should ensure stop mode is not entered while there is a character being transmitted out of or received into the sci module. 14.3.5.3 loop mode when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system problems. in this mode, the transmitter output is internally connected to the receiver input and the rxd pin is not used by the sci, so it reverts to a general-purpose port i/o pin. 14.3.5.4 single-wire operation when loops = 1, the rsrc bit in the same register chooses between loop mode (rsrc = 0) or single-wire mode (rsrc = 1). single-wire mode is used to implement a half-duplex serial connection. the receiver is internally connected to the transmitter output and to the txd pin. the rxd pin is not used and reverts to a general-purpose port i/o pin. in single-wire mode, the txdir bit in scixc3 controls the direction of serial data on the txd pin. when txdir = 0, the txd pin is an input to the sci receiver and the transmitter is temporarily disconnected from the txd pin so an external device can send serial data to the receiver. when txdir = 1, the txd pin is an output driven by the transmitter. in single-wire mode, the internal loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the transmitter.
chapter 14 serial communications interface (s08sciv4) mc9s08de60 series data sheet, rev. 3 308 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 309 chapter 15 real-time counter (s08rtcv1) 15.1 introduction the rtc module consists of one 8-bit counter, one 8-bit comparator, several binary-based and decimal-based prescaler dividers, three clock sources, and one programmable periodic interrupt. this module can be used for time-of-day, calendar or any task scheduling functions. it can also serve as a cyclic wake up from low power modes without the need of external components. all devices in the mc9s08de60 series feature the rtc. 15.1.1 rtc clock signal names references to erclk and irclk in this chapter correspond to signals mcgerclk and mcgirclk, respectively.
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 310 freescale semiconductor figure 15-1. mc9s08de60/32 block diagram emphasizing the rtc module analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc 6-channel timer/pwm module (tpm1) hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) 2-channel timer/pwm module (tpm2) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf3/tpm2clk/sda ptf4/acmp2+ ptf5/acmp2- ptf2/tpm1clk/scl ptf1/rxd2 ptf0/txd2 port f ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area exacting lexica user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0 MC9S08DE32 = 32k
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 311 15.1.2 features features of the rtc module include: 8-bit up-counter 8-bit modulo match limit software controllable periodic interrupt on match three software selectable clock sources for input to prescaler with selectable binary-based and decimal-based divider values 1-khz internal low-power oscillator (lpo) external clock (erclk) 32-khz internal clock (irclk) 15.1.3 modes of operation this section de?es the operation in stop, wait and background debug modes. 15.1.3.1 wait mode the rtc continues to run in wait mode if enabled before executing the appropriate instruction. therefore, the rtc can bring the mcu out of wait mode if the real-time interrupt is enabled. for lowest possible current consumption, the rtc should be stopped by software if not needed as an interrupt source during wait mode. 15.1.3.2 stop modes the rtc continues to run in stop2 or stop3 mode if the rtc is enabled before executing the stop instruction. therefore, the rtc can bring the mcu out of stop modes with no external components, if the real-time interrupt is enabled. the lpo clock can be used in stop2 and stop3 modes. erclk and irclk clocks are only available in stop3 mode. power consumption is lower when all clock sources are disabled, but in that case, the real-time interrupt cannot wake up the mcu from stop modes. 15.1.3.3 active background mode the rtc suspends all counting during active background mode until the microcontroller returns to normal user operating mode. counting resumes from the suspended value as long as the rtcmod register is not written and the rtcps and rtclks bits are not altered.
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 312 freescale semiconductor 15.1.4 block diagram the block diagram for the rtc module is shown in figure 15-2 . figure 15-2. real-time counter (rtc) block diagram 15.2 external signal description the rtc does not include any off-chip signals. 15.3 register de?ition the rtc includes a status and control register, an 8-bit counter register, and an 8-bit modulo register. refer to the direct-page register summary in the memory section of this document for the absolute address assignments for all rtc registers.this section refers to registers and control bits only by their names and relative address offsets. table 15-1 is a summary of rtc registers. table 15-1. rtc register summary name 765 4 3210 rtcsc r rtif rtclks rtie rtcps w rtccnt r rtccnt w rtcmod r rtcmod w clock source select prescaler divide-by 8-bit counter (rtccnt) 8-bit modulo (rtcmod) 8-bit comparator rtif rtie background v dd rtc interrupt request d q r e lpo rtc clock mode erclk irclk rtclks write 1 to rtif rtcps rtclks[0]
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 313 15.3.1 rtc status and control register (rtcsc) rtcsc contains the real-time interrupt status ?g (rtif), the clock select bits (rtclks), the real-time interrupt enable bit (rtie), and the prescaler select bits (rtcps). 7 654 3 210 r rtif rtclks rtie rtcps w reset: 0 0 0 0 0 0 0 0 figure 15-3. rtc status and control register (rtcsc) table 15-2. rtcsc field descriptions field description 7 rtif real-time interrupt flag this status bit indicates the rtc counter register reached the value in the rtc modulo register. writing a logic 0 has no effect. writing a logic 1 clears the bit and the real-time interrupt request. reset clears rtif. 0 rtc counter has not reached the value in the rtc modulo register. 1 rtc counter has reached the value in the rtc modulo register. 6 5 rtclks real-time clock source select. these two read/write bits select the clock source input to the rtc prescaler. changing the clock source clears the prescaler and rtccnt counters. when selecting a clock source, ensure that the clock source is properly enabled (if applicable) to ensure correct operation of the rtc. reset clears rtclks. 00 real-time clock source is the 1-khz low power oscillator (lpo) 01 real-time clock source is the external clock (erclk) 1x real-time clock source is the internal clock (irclk) 4 rtie real-time interrupt enable. this read/write bit enables real-time interrupts. if rtie is set, then an interrupt is generated when rtif is set. reset clears rtie. 0 real-time interrupt requests are disabled. use software polling. 1 real-time interrupt requests are enabled. 3? rtcps real-time clock prescaler select. these four read/write bits select binary-based or decimal-based divide-by values for the clock source. see table 15-3 . changing the prescaler value clears the prescaler and rtccnt counters. reset clears rtcps. table 15-3. rtc prescaler divide-by values rtclks[0] rtcps 01 2 3 45678 9 101112131415 0 off 2 3 2 5 2 6 2 7 2 8 2 9 2 10 12 2 2 10 2 4 10 2 5x10 2 10 3 1 off 2 10 2 11 2 12 2 13 2 14 2 15 2 16 10 3 2x10 3 5x10 3 10 4 2x10 4 5x10 4 10 5 2x10 5
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 314 freescale semiconductor 15.3.2 rtc counter register (rtccnt) rtccnt is the read-only value of the current rtc count of the 8-bit counter. 15.3.3 rtc modulo register (rtcmod) 15.4 functional description the rtc is composed of a main 8-bit up-counter with an 8-bit modulo register, a clock source selector, and a prescaler block with binary-based and decimal-based selectable values. the module also contains software selectable interrupt logic. after any mcu reset, the counter is stopped and reset to 0x00, the modulus register is set to 0x00, and the prescaler is off. the 1-khz internal oscillator clock is selected as the default clock source. to start the prescaler, write any value other than zero to the prescaler select bits (rtcps). three clock sources are software selectable: the low power oscillator clock (lpo), the external clock (erclk), and the internal clock (irclk). the rtc clock select bits (rtclks) select the desired clock source. if a different value is written to rtclks, the prescaler and rtccnt counters are reset to 0x00. 7 654 3 210 r rtccnt w reset: 0 0 0 0 0 0 0 0 figure 15-4. rtc counter register (rtccnt) table 15-4. rtccnt field descriptions field description 7:0 rtccnt rtc count. these eight read-only bits contain the current value of the 8-bit counter. writes have no effect to this register. reset, writing to rtcmod, or writing different values to rtclks and rtcps clear the count to 0x00. 7 654 3 210 r rtcmod w reset: 0 0 0 0 0 0 0 0 figure 15-5. rtc modulo register (rtcmod) table 15-5. rtcmod field descriptions field description 7:0 rtcmod rtc modulo. these eight read/write bits contain the modulo value used to reset the count to 0x00 upon a compare match and set the rtif status bit. a value of 0x00 sets the rtif bit on each rising edge of the prescaler output. writing to rtcmod resets the prescaler and the rtccnt counters to 0x00. reset sets the modulo to 0x00.
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 315 rtcps and the rtclks[0] bit select the desired divide-by value. if a different value is written to rtcps, the prescaler and rtccnt counters are reset to 0x00. table 15-6 shows different prescaler period values. the rtc modulo register (rtcmod) allows the compare value to be set to any value from 0x00 to 0xff. when the counter is active, the counter increments at the selected rate until the count matches the modulo value. when these values match, the counter resets to 0x00 and continues counting. the real-time interrupt ?g (rtif) is set when a match occurs. the ?g sets on the transition from the modulo value to 0x00. writing to rtcmod resets the prescaler and the rtccnt counters to 0x00. the rtc allows for an interrupt to be generated when rtif is set. to enable the real-time interrupt, set the real-time interrupt enable bit (rtie) in rtcsc. rtif is cleared by writing a 1 to rtif. 15.4.1 rtc operation example this section shows an example of the rtc operation as the counter reaches a matching value from the modulo register. table 15-6. prescaler period rtcps 1-khz internal clock (rtclks = 00) 1-mhz external clock (rtclks = 01) 32-khz internal clock (rtclks = 10) 32-khz internal clock (rtclks = 11) 0000 off off off off 0001 8 ms 1.024 ms 250 s 32 ms 0010 32 ms 2.048 ms 1 ms 64 ms 0011 64 ms 4.096 ms 2 ms 128 ms 0100 128 ms 8.192 ms 4 ms 256 ms 0101 256 ms 16.4 ms 8 ms 512 ms 0110 512 ms 32.8 ms 16 ms 1.024 s 0111 1.024 s 65.5 ms 32 ms 2.048 s 1000 1 ms 1 ms 31.25 s 31.25 ms 1001 2 ms 2 ms 62.5 s 62.5 ms 1010 4 ms 5 ms 125 s 156.25 ms 1011 10 ms 10 ms 312.5 s 312.5 ms 1100 16 ms 20 ms 0.5 ms 0.625 s 1101 0.1 s 50 ms 3.125 ms 1.5625 s 1110 0.5 s 0.1 s 15.625 ms 3.125 s 1111 1 s 0.2 s 31.25 ms 6.25 s
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 316 freescale semiconductor figure 15-6. rtc counter over?w example in the example of figure 15-6 , the selected clock source is the 1-khz internal oscillator clock source. the prescaler (rtcps) is set to 0xa or divide-by-4. the modulo value in the rtcmod register is set to 0x55. when the counter, rtccnt, reaches the modulo value of 0x55, the counter over?ws to 0x00 and continues counting. the real-time interrupt ?g, rtif, sets when the counter value changes from 0x55 to 0x00. a real-time interrupt is generated when rtif is set, if rtie is set. 15.5 initialization/application information this section provides example code to give some basic direction to a user on how to initialize and con?ure the rtc module. the example software is implemented in c language. the example below shows how to implement time of day with the rtc using the 1-khz clock source to achieve the lowest possible power consumption. because the 1-khz clock source is not as accurate as a crystal, software can be added for any adjustments. for accuracy without adjustments at the expense of additional power consumption, the external clock (erclk) or the internal clock (irclk) can be selected with appropriate prescaler and modulo values. /* initialize the elapsed time counters */ seconds = 0; minutes = 0; hours = 0; days=0; /* configure rtc to interrupt every 1 second from 1-khz clock source */ rtcmod.byte = 0x00; rtcsc.byte = 0x1f; /********************************************************************** function name : rtc_isr notes : interrupt service routine for rtc module. **********************************************************************/ 0x55 0x55 0x54 0x53 0x52 0x00 0x01 rtcmod rtif rtccnt rtc clock (rtcps = 0xa) internal 1-khz clock source
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 317 #pragma trap_proc void rtc_isr(void) { /* clear the interrupt flag */ rtcsc.byte = rtcsc.byte | 0x80; /* rtc interrupts every 1 second */ seconds++; /* 60 seconds in a minute */ if (seconds > 59){ minutes++; seconds = 0; } /* 60 minutes in an hour */ if (minutes > 59){ hours++; minutes = 0; } /* 24 hours in a day */ if (hours > 23){ days ++; hours = 0; }
chapter 15 real-time counter (s08rtcv1) mc9s08de60 series data sheet, rev. 3 318 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 319 chapter 16 timer pulse-width modulator (s08tpmv3) note this chapter refers to s08tpm version 3, which applies to the 0m74k and newer mask sets of this device. 3m05c and older mask set devices use s08tpm version 2. if your device uses mask 3m05c or older, please refer to appendix b, ?imer pulse-width modulator (tpmv2) on page 393 for information pertaining to that module. 16.1 introduction the tpm is a one-to-eight-channel timer system which supports traditional input capture, output compare, or edge-aligned pwm on each channel. a control bit allows the tpm to be con?ured such that all channels may be used for center-aligned pwm functions. timing functions are based on a 16-bit counter with prescaler and modulo features to control frequency and range (period between over?ws) of the time reference. this timing system is ideally suited for a wide range of control applications, and the center-aligned pwm capability extends the ?ld of application to motor control in small appliances. the tpm uses one input/output (i/o) pin per channel, tpmxchn, where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 0?). the tpm shares its i/o pins with general-purpose i/o port pins (refer to the pins and connections chapter for more information). mc9s08de60 series mcus have two tpm modules. in all packages, tpm2 is 2-channel and tpm1 is 6-channel.
chapter 16 timer pulse-width modulator (s08tpmv3) mc9s08de60 series data sheet, rev. 3 320 freescale semiconductor figure 16-1. mc9s08de60/32 block diagram emphasizing the tpm modules and pins analog comparator (acmp1) acmp1o acmp1- acmp1+ v ss v dd iic module (iic) serial peripheral interface module (spi) user flash user ram mc9s08de60 = 60k hcs08 core cpu bdc hcs08 system control resets and interrupts modes of operation power management voltage regulator cop irq lvd oscillator (xosc) multi-purpose clock generator reset v refl v refh analog-to-digital converter (adc) mc9s08de60 = 4k 24-channel, 12-bit bkgd/ms interface (sci1) serial communications sda scl miso ss spsck txd1 rxd1 xtal extal 8 (mcg) real-time counter (rtc) debug module (dbg) irq pta3/pia3/adp3/acmp1o pta4/pia4/adp4 pta5/pia5/adp5 pta2/pia2/adp2/acmp1- pta1/pia1/adp1/acmp1+ pta0/pia0/adp0/mclk port a pta6/pia6/adp6 pta7/pia7/adp7/irq mosi ptb3/pib3/adp11 ptb4/pib4/adp12 ptb5/pib5/adp13 ptb2/pib2/adp10 ptb1/pib1/adp9 ptb0/pib0/adp8 port b ptb6/pib6/adp14 ptb7/pib7/adp15 ptc3/adp19 ptc4/adp20 ptc5/adp21 ptc2/adp18 ptc1/adp17 ptc0/adp16 port c ptc6/adp22 ptc7/adp23 pte3/spsck pte4/scl/mosi pte5/sda/miso pte2/ ss pte1/rxd1 pte0/txd1 port e pte6/txd2/txcan pte7/rxd2/rxcan ptf4/acmp2+ ptf5/acmp2- ptf1/rxd2 ptf0/txd2 ptf6/acmp2o ptf7 ptg1/xtal ptg2 ptg3 port g ptg4 ptg5 ptg0/extal v ss v dd v ssa v dda bkp int analog comparator (acmp2) acmp2o acmp2- acmp2+ interface (sci2) serial communications txd2 rxd2 network (mscan) controller area txcan rxcan user eeprom mc9s08de60 = 2k adp7-adp0 adp15-adp8 adp23-adp16 MC9S08DE32 = 32k 6-channel timer/pwm module (tpm1) 2-channel timer/pwm module (tpm2) ptd3/pid3/tpm1ch1 ptd4/pid4/tpm1ch2 ptd5/pid5/tpm1ch3 ptd2/pid2/tpm1ch0 ptd1/pid1/tpm2ch1 ptd0/pid0/tpm2ch0 port d ptd6/pid6/tpm1ch4 ptd7/pid7/tpm1ch5 ptf3/tpm2clk/sda ptf2/tpm1clk/scl port f 6 tpm1ch5 - tpm2ch1, tpm2ch0 tpm2clk tpm1clk tpm1ch0
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 321 16.1.1 features the tpm includes these distinctive features: one to eight channels: each channel may be input capture, output compare, or edge-aligned pwm rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action selectable polarity on pwm outputs module may be con?ured for buffered, center-aligned pulse-width-modulation (cpwm) on all channels timer clock source selectable as prescaled bus clock, ?ed system clock, or an external clock pin prescale taps for divide-by 1, 2, 4, 8, 16, 32, 64, or 128 fixed system clock source are synchronized to the bus clock by an on-chip synchronization circuit external clock pin may be shared with any timer channel pin or a separated input pin 16-bit free-running or modulo up/down count operation timer system enable one interrupt per channel plus terminal count interrupt 16.1.2 modes of operation in general, tpm channels may be independently con?ured to operate in input capture, output compare, or edge-aligned pwm modes. a control bit allows the whole tpm (all channels) to switch to center-aligned pwm mode. when center-aligned pwm mode is selected, input capture, output compare, and edge-aligned pwm functions are not available on any channels of this tpm module. when the microcontroller is in active bdm background or bdm foreground mode, the tpm temporarily suspends all counting until the microcontroller returns to normal user operating mode. during stop mode, all system clocks, including the main oscillator, are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. provided the tpm does not need to produce a real time reference or provide the interrupt source(s) needed to wake the mcu from wait mode, the user can save power by disabling tpm functions before entering wait mode. input capture mode when a selected edge event occurs on the associated mcu pin, the current value of the 16-bit timer counter is captured into the channel value register and an interrupt ?g bit is set. rising edges, falling edges, any edge, or no edge (disable channel) may be selected as the active edge which triggers the input capture. output compare mode when the value in the timer counter register matches the channel value register, an interrupt ?g bit is set, and a selected output action is forced on the associated mcu pin. the output compare action may be selected to force the pin to zero, force the pin to one, toggle the pin, or ignore the pin (used for software timing functions).
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 322 freescale semiconductor edge-aligned pwm mode the value of a 16-bit modulo register plus 1 sets the period of the pwm output signal. the channel value register sets the duty cycle of the pwm output signal. the user may also choose the polarity of the pwm output signal. interrupts are available at the end of the period and at the duty-cycle transition point. this type of pwm signal is called edge-aligned because the leading edges of all pwm signals are aligned with the beginning of the period, which is the same for all channels within a tpm. center-aligned pwm mode twice the value of a 16-bit modulo register sets the period of the pwm output, and the channel-value register sets the half-duty-cycle duration. the timer counter counts up until it reaches the modulo value and then counts down until it reaches zero. as the count matches the channel value register while counting down, the pwm output becomes active. when the count matches the channel value register while counting up, the pwm output becomes inactive. this type of pwm signal is called center-aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero. this type of pwm is required for types of motors used in small appliances. this is a high-level description only. detailed descriptions of operating modes are in later sections. 16.1.3 block diagram the tpm uses one input/output (i/o) pin per channel, tpmxchn (timer channel n) where n is the channel number (1-8). the tpm shares its i/o pins with general purpose i/o port pins (refer to i/o pin descriptions in full-chip speci?ation for the speci? chip implementation). figure 16-2 shows the tpm structure. the central component of the tpm is the 16-bit counter that can operate as a free-running counter or a modulo up/down counter. the tpm counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned pwm functions. the timer counter modulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter (the values 0x0000 or 0xffff effectively make the counter free running). software can read the counter value at any time without affecting the counting sequence. any write to either half of the tpmxcnt counter resets the counter, regardless of the data value written.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 323 figure 16-2. tpm block diagram prescale and select 16-bit comparator ps2:ps1:ps0 tof toie inter- 16-bit counter rupt logic 16-bit comparator 16-bit latch els0b els0a port channel 0 ch0ie ch0f logic inter- rupt logic cpwms ms0b ms0a counter reset clksb:clksa 1, 2, 4, 8, 16, 32, 64, bus clock fixed system clock external clock sync 16-bit comparator 16-bit latch channel 1 els1b els1a ch1ie ch1f internal bus port logic inter- rupt logic ms1b ms1a 16-bit comparator 16-bit latch channel 7 els7b els7a ch7ie ch7f port logic inter- rupt logic ms7b ms7a up to 8 channels clock source select off, bus, fixed system clock, ext or 128 tpmxmodh:tpmxmodl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxch0 tpmxch1 tpmxc7vh:tpmxc7vl tpmxch7
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 324 freescale semiconductor the tpm channels are programmable independently as input capture, output compare, or edge-aligned pwm channels. alternately, the tpm can be con?ured to produce cpwm outputs on all channels. when the tpm is con?ured for cpwms, the counter operates as an up/down counter; input capture, output compare, and epwm functions are not practical. if a channel is con?ured as input capture, an internal pullup device may be enabled for that channel. the details of how a module interacts with pin controls depends upon the chip implementation because the i/o pins and associated general purpose i/o controls are not part of the module. refer to the discussion of the i/o port logic in a full-chip speci?ation. because center-aligned pwms are usually used to drive 3-phase ac-induction motors and brushless dc motors, they are typically used in sets of three or six channels. 16.2 signal description table 16-1 shows the user-accessible signals for the tpm. the number of channels may be varied from one to eight. when an external clock is included, it can be shared with the same pin as any tpm channel; however, it could be connected to a separate input pin. refer to the i/o pin descriptions in full-chip speci?ation for the speci? chip implementation. refer to documentation for the full-chip for details about reset states, port connections, and whether there is any pullup device on these pins. tpm channel pins can be associated with general purpose i/o pins and have passive pullup devices which can be enabled with a control bit when the tpm or general purpose i/o controls have con?ured the associated pin as an input. when no tpm function is enabled to use a corresponding pin, the pin reverts to being controlled by general purpose i/o controls, including the port-data and data-direction registers. immediately after reset, no tpm functions are enabled, so all associated pins revert to general purpose i/o control. 16.2.1 detailed signal descriptions this section describes each user-accessible pin signal in detail. although table 16-1 grouped all channel pins together, any tpm pin can be shared with the external clock source signal. since i/o pin logic is not part of the tpm, refer to full-chip documentation for a speci? derivative for more details about the interaction of tpm pin functions and general purpose i/o controls including port data, data direction, and pullup controls. table 16-1. signal properties name function extclk 1 1 when preset, this signal can share any channel pin; however depending upon full-chip implementation, this signal could be connected to a separate external pin. external clock source which may be selected to drive the tpm counter. tpmxchn 2 2 n=channel number (1 to 8) i/o pin associated with tpm channel n
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 325 16.2.1.1 extclk ?external clock source control bits in the timer status and control register allow the user to select nothing (timer disable), the bus-rate clock (the normal default source), a crystal-related clock, or an external clock as the clock which drives the tpm prescaler and subsequently the 16-bit tpm counter. the external clock source is synchronized in the tpm. the bus clock clocks the synchronizer; the frequency of the external source must be no more than one-fourth the frequency of the bus-rate clock, to meet nyquist criteria and allowing for jitter. the external clock signal shares the same pin as a channel i/o pin, so the channel pin will not be usable for channel i/o function when selected as the external clock source. it is the users responsibility to avoid such settings. if this pin is used as an external clock source (clksb:clksa = 1:1), the channel can still be used in output compare mode as a software timer (elsnb:elsna = 0:0). 16.2.1.2 tpmxchn ?tpm channel n i/o pin(s) each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the channel con?uration. the tpm pins share with general purpose i/o pins, where each pin has a port data register bit, and a data direction control bit, and the port has optional passive pullups which may be enabled whenever a port pin is acting as an input. the tpm channel does not control the i/o pin when (elsnb:elsna = 0:0) or when (clksb:clksa = 0:0) so it normally reverts to general purpose i/o control. when cpwms = 1 (and elsnb:elsna not = 0:0), all channels within the tpm are con?ured for center-aligned pwm and the tpmxchn pins are all controlled by the tpm system. when cpwms=0, the msnb:msna control bits determine whether the channel is con?ured for input capture, output compare, or edge-aligned pwm. when a channel is con?ured for input capture (cpwms=0, msnb:msna = 0:0 and elsnb:elsna not = 0:0), the tpmxchn pin is forced to act as an edge-sensitive input to the tpm. elsnb:elsna control bits determine what polarity edge or edges will trigger input-capture events. a synchronizer based on the bus clock is used to synchronize input edges to the bus clock. this implies the minimum pulse width?hat can be reliably detected?n an input capture pin is four bus clock periods (with ideal clock pulses as near as two bus clocks can be detected). tpm uses this pin as an input capture input to override the port data and data direction controls for the same pin. when a channel is con?ured for output compare (cpwms=0, msnb:msna = 0:1 and elsnb:elsna not = 0:0), the associated data direction control is overridden, the tpmxchn pin is considered an output controlled by the tpm, and the elsnb:elsna control bits determine how the pin is controlled. the remaining three combinations of elsnb:elsna determine whether the tpmxchn pin is toggled, cleared, or set each time the 16-bit channel value register matches the timer counter. when the output compare toggle mode is initially selected, the previous value on the pin is driven out until the next output compare event?hen the pin is toggled.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 326 freescale semiconductor when a channel is con?ured for edge-aligned pwm (cpwms=0, msnb=1 and elsnb:elsna not = 0:0), the data direction is overridden, the tpmxchn pin is forced to be an output controlled by the tpm, and elsna controls the polarity of the pwm output signal on the pin. when elsnb:elsna=1:0, the tpmxchn pin is forced high at the start of each new period (tpmxcnt=0x0000), and the pin is forced low when the channel value register matches the timer counter. when elsna=1, the tpmxchn pin is forced low at the start of each new period (tpmxcnt=0x0000), and the pin is forced high when the channel value register matches the timer counter. figure 16-3. high-true pulse of an edge-aligned pwm figure 16-4. low-true pulse of an edge-aligned pwm chnf bit tof bit 0... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmxchn chnf bit tof bit 0... 1 2 345 6 780 12... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmxchn
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 327 when the tpm is con?ured for center-aligned pwm (and elsnb:elsna not = 0:0), the data direction for all channels in this tpm are overridden, the tpmxchn pins are forced to be outputs controlled by the tpm, and the elsna bits control the polarity of each tpmxchn output. if elsnb:elsna=1:0, the corresponding tpmxchn pin is cleared when the timer counter is counting up, and the channel value register matches the timer counter; the tpmxchn pin is set when the timer counter is counting down, and the channel value register matches the timer counter. if elsna=1, the corresponding tpmxchn pin is set when the timer counter is counting up and the channel value register matches the timer counter; the tpmxchn pin is cleared when the timer counter is counting down and the channel value register matches the timer counter. figure 16-5. high-true pulse of a center-aligned pwm figure 16-6. low-true pulse of a center-aligned pwm chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 t pmxcnth:tpmxcntl tpmxchn chnf bit tof bit ... 78 765 4 321 012 34 56 78 76 5 ... tpmxmodh:tpmxmodl = 0x0008 tpmxcnvh:tpmxcnvl = 0x0005 t pmxcnth:tpmxcntl tpmxchn
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 328 freescale semiconductor 16.3 register de?ition this section consists of register descriptions in address order. 16.3.1 tpm status and control register (tpmxsc) tpmxsc contains the over?w status ?g and control bits used to con?ure the interrupt enable, tpm con?uration, clock source, and prescale factor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w0 reset 00000000 figure 16-7. tpm status and control register (tpmxsc) table 16-2. tpmxsc field descriptions field description 7 tof timer over?w ?g. this read/write ?g is set when the tpm counter resets to 0x0000 after reaching the modulo value programmed in the tpm counter modulo registers. clear tof by reading the tpm status and control register when tof is set and then writing a logic 0 to tof. if another tpm over?w occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. this is done so a tof interrupt request cannot be lost during the clearing sequence for a previous tof. reset clears tof. writing a logic 1 to tof has no effect. 0 tpm counter has not reached modulo value or over?w 1 tpm counter has over?wed 6 toie timer over?w interrupt enable. this read/write bit enables tpm over?w interrupts. if toie is set, an interrupt is generated when tof equals one. reset clears toie. 0 tof interrupts inhibited (use for software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select. when present, this read/write bit selects cpwm operating mode. by default, the tpm operates in up-counting mode for input capture, output compare, and edge-aligned pwm functions. setting cpwms recon?ures the tpm to operate in up/down counting mode for cpwm functions. reset clears cpwms. 0 all channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each channels status and control register. 1 all channels operate in center-aligned pwm mode. 4? clks[b:a] clock source selects. as shown in table 16-3 , this 2-bit ?ld is used to disable the tpm system or select one of three clock sources to drive the counter prescaler. the ?ed system clock source is only meaningful in systems with a pll-based or fll-based system clock. when there is no pll or fll, the ?ed-system clock source is the same as the bus rate clock. the external source is synchronized to the bus clock by tpm module, and the ?ed system clock source (when a pll or fll is present) is synchronized to the bus clock by an on-chip synchronization circuit. when a pll or fll is present but not enabled, the ?ed-system clock source is the same as the bus-rate clock. 2? ps[2:0] prescale factor select. this 3-bit ?ld selects one of 8 division factors for the tpm clock input as shown in table 16-4 . this prescaler is located after any clock source synchronization or clock source selection so it affects the clock source selected to drive the tpm system. the new prescale factor will affect the clock source on the next system clock cycle after the new value is updated into the register bits.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 329 16.3.2 tpm-counter registers (tpmxcnth:tpmxcntl) the two read-only tpm counter registers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other half is read. this allows coherent 16-bit reads in either big-endian or little-endian order which makes this more friendly to various compiler implementations. the coherency mechanism is automatically restarted by an mcu reset or any write to the timer status/control register (tpmxsc). reset clears the tpm counter registers. writing any value to tpmxcnth or tpmxcntl also clears the tpm counter (tpmxcnth:tpmxcntl) and resets the coherency mechanism, regardless of the data involved in the write. table 16-3. tpm-clock-source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (tpm counter disable) 01 bus rate clock 10 fixed system clock 11 external source table 16-4. prescale factor selection ps2:ps1:ps0 tpm clock source divided-by 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter reset 00000000 figure 16-8. tpm counter register high (tpmxcnth)
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 330 freescale semiconductor when bdm is active, the timer counter is frozen (this is the value that will be read by user); the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active, even if one or both counter halves are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. in bdm mode, writing any value to tpmxsc, tpmxcnth or tpmxcntl registers resets the read coherency mechanism of the tpmxcnth:l registers, regardless of the data involved in the write. 16.3.3 tpm counter modulo registers (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock, and the over?w ?g (tof) becomes set. writing to tpmxmodh or tpmxmodl inhibits the tof bit and over?w interrupts until the other byte is written. reset sets the tpm counter modulo registers to 0x0000 which results in a free running timer counter (modulo disabled). writing to either byte (tpmxmodh or tpmxmodl) latches the value into a buffer and the registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), then the registers are updated when the second byte is written if (clksb:clksa not = 0:0), then the registers are updated after both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff the latching mechanism may be manually reset by writing to the tpmxsc address (whether bdm is active or not). when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxsc register) such that the buffer latches remain in the state they were in when the bdm became active, even if one or both halves of the modulo register are written while bdm is active. any write to the modulo registers bypasses the buffer latches and directly writes to the modulo register while bdm is active. 76543210 r bit 7 654321 bit 0 w any write to tpmxcntl clears the 16-bit counter reset 00000000 figure 16-9. tpm counter register low (tpmxcntl) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure 16-10. tpm counter modulo register high (tpmxmodh)
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 331 reset the tpm counter before writing to the tpm modulo registers to avoid confusion about when the ?st counter over?w will occur. 16.3.4 tpm channel n status and control register (tpmxcnsc) tpmxcnsc contains the channel-interrupt-status ?g and control bits used to con?ure the interrupt enable, channel con?uration, and pin function. 76543210 r bit 7 654321 bit 0 w reset 00000000 76543210 r chnf chnie msnb msna elsnb elsna 00 w0 reset 00000000 = unimplemented or reserved figure 16-12. tpm channel n status and control register (tpmxcnsc) table 16-5. tpmxcnsc field descriptions field description 7 chnf channel n ?g. when channel n is an input-capture channel, this read/write bit is set when an active edge occurs on the channel n pin. when channel n is an output compare or edge-aligned/center-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. when channel n is an edge-aligned/center-aligned pwm channel and the duty cycle is set to 0% or 100%, chnf will not be set even when the value in the tpm counter registers matches the value in the tpm channel n value registers. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a logic 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf remains set after the clear sequence completed for the earlier chnf. this is done so a chnf interrupt request cannot be lost due to clearing a previous chnf. reset clears the chnf bit. writing a logic 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event on channel n 6 chnie channel n interrupt enable. this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use for software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n. when cpwms=0, msnb=1 con?ures tpm channel n for edge-aligned pwm mode. refer to the summary of channel mode and setup controls in table 16-6 .
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 332 freescale semiconductor 16.3.5 tpm channel value registers (tpmxcnvh:tpmxcnvl) these read/write registers contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pwm functions. the channel registers are cleared by reset. 4 msna mode select a for tpm channel n. when cpwms=0 and msnb=0, msna con?ures tpm channel n for input-capture mode or output compare mode. refer to table 16-6 for a summary of channel mode and setup controls. note: if the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. 3? elsnb elsna edge/level select bits. depending upon the operating mode for the timer channel as set by cpwms:msnb:msna and shown in table 16-6 , these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 con?ures the related timer pin as a general purpose i/o pin not related to any timer functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin. table 16-6. mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode con?uration x xx 00 pin not used for tpm - revert to general purpose i/o or other peripheral control 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 01 output compare toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) table 16-5. tpmxcnsc field descriptions (continued) field description
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 333 in input capture mode, reading either byte (tpmxcnvh or tpmxcnvl) latches the contents of both bytes into a buffer where they remain latched until the other half is read. this latching mechanism also resets (becomes unlatched) when the tpmxcnsc register is written (whether bdm mode is active or not). any write to the channel registers will be ignored during the input capture mode. when bdm is active, the coherency mechanism is frozen (unless reset by writing to tpmxcnsc register) such that the buffer latches remain in the state they were in when the bdm became active, even if one or both halves of the channel register are read while bdm is active. this assures that if the user was in the middle of reading a 16-bit register when bdm became active, it will read the appropriate value from the other half of the 16-bit value after returning to normal execution. the value read from the tpmxcnvh and tpmxcnvl registers in bdm mode is the value of these registers and not the value of their read buffer. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. after both bytes are written, they are transferred as a coherent 16-bit value into the timer-channel registers according to the value of clksb:clksa bits and the selected mode, so: if (clksb:clksa = 0:0), then the registers are updated when the second byte is written. if (clksb:clksa not = 0:0 and in output compare mode) then the registers are updated after the second byte is written and on the next change of the tpm counter (end of the prescaler counting). if (clksb:clksa not = 0:0 and in epwm or cpwm modes), then the registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. the latching mechanism may be manually reset by writing to the tpmxcnsc register (whether bdm mode is active or not). this latching mechanism allows coherent 16-bit writes in either big-endian or little-endian order which is friendly to various compiler implementations. when bdm is active, the coherency mechanism is frozen such that the buffer latches remain in the state they were in when the bdm became active even if one or both halves of the channel register are written while bdm is active. any write to the channel registers bypasses the buffer latches and directly write to the channel register while bdm is active. the values written to the channel register while bdm is active 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure 16-13. tpm channel value register high (tpmxcnvh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure 16-14. tpm channel value register low (tpmxcnvl)
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 334 freescale semiconductor are used for pwm & output compare operation once normal execution resumes. writes to the channel registers while bdm is active do not interfere with partial completion of a coherency sequence. after the coherency mechanism has been fully exercised, the channel registers are updated using the buffered values written (while bdm was not active) by the user. 16.4 functional description all tpm functions are associated with a central 16-bit counter which allows ?xible selection of the clock source and prescale factor. there is also a 16-bit modulo register associated with the main counter. the cpwms control bit chooses between center-aligned pwm operation for all channels in the tpm (cpwms=1) or general purpose timing functions (cpwms=0) where each channel can independently be con?ured to operate in input capture, output compare, or edge-aligned pwm mode. the cpwms control bit is located in the main tpm status and control register because it affects all channels within the tpm and in?ences the way the main counter operates. (in cpwm mode, the counter changes to an up/down mode rather than the up-counting mode used for general purpose timer functions.) the following sections describe the main counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend upon the operating mode, these topics will be covered in the associated mode explanation sections. 16.4.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, end-of-count over?w, up-counting vs. up/down counting, and manual counter reset. 16.4.1.1 counter clock source the 2-bit ?ld, clksb:clksa, in the timer status and control register (tpmxsc) selects one of three possible clock sources or off (which effectively disables the tpm). see table 16-3 . after any mcu reset, clksb:clksa=0:0 so no clock source is selected, and the tpm is in a very low power state. these control bits may be read or written at any time and disabling the timer (writing 00 to the clksb:clksa ?ld) does not affect the values in the counter or other timer registers.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 335 the bus rate clock is the main system bus clock for the mcu. this clock source requires no synchronization because it is the clock that is used for all internal mcu activities including operation of the cpu and buses. in mcus that have no pll and fll or the pll and fll are not engaged, the ?ed system clock source is the same as the bus-rate-clock source, and it does not go through a synchronizer. when a pll or fll is present and engaged, a synchronizer is required between the crystal divided-by two clock source and the timer counter so counter transitions will be properly aligned to bus-clock transitions. a synchronizer will be used at chip level to synchronize the crystal-related source clock to the bus clock. the external clock source may be connected to any tpm channel pin. this clock source always has to pass through a synchronizer to assure that counter transitions are properly aligned to bus clock transitions. the bus-rate clock drives the synchronizer; therefore, to meet nyquist criteria even with jitter, the frequency of the external clock source must not be faster than the bus rate divided-by four. with ideal clocks the external clock can be as fast as bus clock divided by four. when the external clock source shares the tpm channel pin, this pin should not be used for other channel timing functions. for example, it would be ambiguous to con?ure channel 0 for input capture when the tpm channel 0 pin was also being used as the timer external clock source. (it is the users responsibility to avoid such settings.) the tpm channel could still be used in output compare mode for software timing functions (pin controls set not to affect the tpm channel pin). 16.4.1.2 counter over?w and modulo reset an interrupt ?g and enable are associated with the 16-bit main counter. the ?g (tof) is a software-accessible indication that the timer counter has over?wed. the enable signal selects between software polling (toie=0) where no hardware interrupt is generated, or interrupt-driven operation (toie=1) where a static hardware interrupt is generated whenever the tof ?g is equal to one. the conditions causing tof to become set depend on whether the tpm is con?ured for center-aligned pwm (cpwms=1). in the simplest mode, there is no modulus limit and the tpm is not in cpwms=1 mode. in this case, the 16-bit timer counter counts from 0x0000 through 0xffff and over?ws to 0x0000 on the next counting clock. tof becomes set at the transition from 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the tpm is in center-aligned pwm mode (cpwms=1), the tof ?g gets set as the counter changes direction at the end of the count value set in the modulus register (that is, at the transition from the value set in the modulus register to the next lower count value). this corresponds to the end of a pwm period (the 0x0000 count value corresponds to the center of a period). table 16-7. tpm clock source selection clksb:clksa tpm clock source to prescaler input 00 no clock selected (tpm counter disabled) 01 bus rate clock 10 fixed system clock 11 external source
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 336 freescale semiconductor 16.4.1.3 counting modes the main timer counter has two counting modes. when center-aligned pwm is selected (cpwms=1), the counter operates in up/down counting mode. otherwise, the counter operates as a simple up counter. as an up counter, the timer counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is speci?d, the counter counts up from 0x0000 through its terminal count and then down to 0x0000 where it changes back to up counting. both 0x0000 and the terminal count value are normal length counts (one timer clock period long). in this mode, the timer over?w ?g (tof) becomes set at the end of the terminal-count period (as the count changes to the next lower count value). 16.4.1.4 manual counter reset the main timer counter can be manually reset at any time by writing any value to either half of tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only half of the counter was read before resetting the count. 16.4.2 channel mode selection provided cpwms=0, the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and edge-aligned pwm. 16.4.2.1 input capture mode with the input-capture function, the tpm can capture the time at which an external event occurs. when an active edge occurs on the pin of an input-capture channel, the tpm latches the contents of the tpm counter into the channel-value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. in input capture mode, the tpmxcnvh and tpmxcnvl registers are read only. when either half of the 16-bit capture register is read, the other half is latched into a buffer to support coherent 16-bit accesses in big-endian or little-endian order. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an input capture event sets a ?g bit (chnf) which may optionally generate a cpu interrupt request. while in bdm, the input capture function works as con?ured by the user. when an external event occurs, the tpm latches the contents of the tpm counter (which is frozen because of the bdm mode) into the channel value registers and sets the ?g bit. 16.4.2.2 output compare mode with the output-compare function, the tpm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter reaches the value in the channel-value registers of an output-compare channel, the tpm can set, clear, or toggle the channel pin.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 337 in output compare mode, values are transferred to the corresponding timer channel registers only after both 8-bit halves of a 16-bit register have been written and according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), the registers are updated when the second byte is written if (clksb:clksa not = 0:0), the registers are updated at the next change of the tpm counter (end of the prescaler counting) after the second byte is written. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an output compare event sets a ?g bit (chnf) which may optionally generate a cpu-interrupt request. 16.4.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counting mode of the timer counter (cpwms=0) and can be used when other channels in the same tpm are con?ured for input capture or output compare functions. the period of this pwm signal is determined by the value of the modulus register (tpmxmodh:tpmxmodl) plus 1. the duty cycle is determined by the setting in the timer channel register (tpmxcnvh:tpmxcnvl). the polarity of this pwm signal is determined by the setting in the elsna control bit. 0% and 100% duty cycle cases are possible. the output compare value in the tpm channel registers determines the pulse width (duty cycle) of the pwm signal ( figure 16-15 ). the time between the modulus over?w and the output compare is the pulse width. if elsna=0, the counter over?w forces the pwm signal high, and the output compare forces the pwm signal low. if elsna=1, the counter over?w forces the pwm signal low, and the output compare forces the pwm signal high. figure 16-15. pwm period and pulse width (elsna=0) when the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved by setting the timer-channel register (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting. this implies that the modulus setting must be less than 0xffff in order to get 100% duty cycle. because the tpm may be used in an 8-bit mcu, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxcnvh and tpmxcnvl, actually write to buffer registers. in edge-aligned pwm mode, values are transferred to the corresponding timer-channel registers according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), the registers are updated when the second byte is written if (clksb:clksa not = 0:0), the registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if period pulse width overflow overflow overflow output compare output compare output compare tpmxchn
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 338 freescale semiconductor the tpm counter is a free-running counter then the update is made when the tpm counter changes from 0xfffe to 0xffff. 16.4.2.4 center-aligned pwm mode this type of pwm output uses the up/down counting mode of the timer counter (cpwms=1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal while the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff because values outside this range can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) period = 2 x (tpmxmodh:tpmxmodl); tpmxmodh:tpmxmodl=0x0001-0x7fff if the channel-value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (non-zero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if you do not need to generate 100% duty cycle). this is not a signi?ant limitation. the resulting period would be much longer than required for normal applications. tpmxmodh:tpmxmodl=0x0000 is a special case that should not be used with center-aligned pwm mode. when cpwms=0, this case corresponds to the counter running free from 0x0000 through 0xffff, but when cpwms=1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. the output compare value in the tpm channel registers (times 2) determines the pulse width (duty cycle) of the cpwm signal ( figure 16-16). if elsna=0, a compare occurred while counting up forces the cpwm output signal low and a compare occurred while counting down forces the output high. the counter counts up until it reaches the modulo setting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure 16-16. cpwm period and pulse width (elsna=0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also required for some types of motor drives. period pulse width count= count= 0 count= output compare (count down) output compare (count up) tpmxchn 2 x tpmxmodh:tpmxmodl 2 x tpmxcnvh:tpmxcnvl tpmxmodh:tpmxmodl tpmxmodh:tpmxmodl
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 339 input capture, output compare, and edge-aligned pwm functions do not make sense when the counter is operating in up/down counting mode so this implies that all active channels within a tpm must be used in cpwm mode when cpwms=1. the tpm may be used in an 8-bit mcu. the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl, actually write to buffer registers. in center-aligned pwm mode, the tpmxcnvh:l registers are updated with the value of their write buffer according to the value of clksb:clksa bits, so: if (clksb:clksa = 0:0), the registers are updated when the second byte is written if (clksb:clksa not = 0:0), the registers are updated after the both bytes were written, and the tpm counter changes from (tpmxmodh:tpmxmodl - 1) to (tpmxmodh:tpmxmodl). if the tpm counter is a free-running counter, the update is made when the tpm counter changes from 0xfffe to 0xffff. when tpmxcnth:tpmxcntl=tpmxmodh:tpmxmodl, the tpm can optionally generate a tof interrupt (at the end of this count). writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo registers. writing to tpmxcnsc cancels any values written to the channel value registers and resets the coherency mechanism for tpmxcnvh:tpmxcnvl. 16.5 reset overview 16.5.1 general the tpm is reset whenever any mcu reset occurs. 16.5.2 description of reset operation reset clears the tpmxsc register which disables clocks to the tpm and disables timer over?w interrupts (toie=0). cpwms, msnb, msna, elsnb, and elsna are all cleared which con?ures all tpm channels for input-capture operation with the associated pins disconnected from i/o pin logic (so all mcu pins related to the tpm revert to general purpose i/o pins). 16.6 interrupts 16.6.1 general the tpm generates an optional interrupt for the main counter over?w and an interrupt for each channel. the meaning of channel interrupts depends on each channels mode of operation. if the channel is con?ured for input capture, the interrupt ?g is set each time the selected input capture edge is recognized. if the channel is con?ured for output compare or pwm modes, the interrupt ?g is set each time the main timer counter matches the value in the 16-bit channel value register.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 340 freescale semiconductor all tpm interrupts are listed in table 16-8 which shows the interrupt name, the name of any local enable that can block the interrupt request from leaving the tpm and getting recognized by the separate interrupt processing logic. the tpm module will provide a high-true interrupt signal. vectors and priorities are determined at chip integration time in the interrupt module so refer to the users guide for the interrupt module or to the chips complete documentation for details. 16.6.2 description of interrupt operation for each interrupt source in the tpm, a ?g bit is set upon recognition of the interrupt condition such as timer over?w, channel-input capture, or output-compare events. this ?g may be read (polled) by software to determine that the action has occurred, or an associated enable bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interrupt will generate whenever the associated interrupt ?g equals one. the users software must perform a sequence of steps to clear the interrupt ?g before returning from the interrupt-service routine. tpm interrupt ?gs are cleared by a two-step process including a read of the ?g bit while it is set (1) followed by a write of zero (0) to the bit. if a new event is detected between these two steps, the sequence is reset and the interrupt ?g remains set after the second step to avoid the possibility of missing the new event. 16.6.2.1 timer over?w interrupt (tof) description the meaning and details of operation for tof interrupts varies slightly depending upon the mode of operation of the tpm system (general purpose timing functions versus center-aligned pwm operation). the ?g is cleared by the two step sequence described above. 16.6.2.1.1 normal case normally tof is set when the timer counter changes from 0xffff to 0x0000. when the tpm is not con?ured for center-aligned pwm (cpwms=0), tof gets set when the timer counter changes from the terminal count (the value in the modulo register) to 0x0000. this case corresponds to the normal meaning of counter over?w. table 16-8. interrupt summary interrupt local enable source description tof toie counter over?w set each time the timer counter reaches its terminal count (at transition to next count value which is usually 0x0000) chnf chnie channel event an input capture or output compare event took place on channel n
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 341 16.6.2.1.2 center-aligned pwm case when cpwms=1, tof gets set when the timer counter changes direction from up-counting to down-counting at the end of the terminal count (the value in the modulo register). in this case the tof corresponds to the end of a pwm period. 16.6.2.2 channel event interrupt description the meaning of channel interrupts depends on the channels current mode (input-capture, output-compare, edge-aligned pwm, or center-aligned pwm). 16.6.2.2.1 input capture events when a channel is con?ured as an input capture channel, the elsnb:elsna control bits select no edge (off), rising edges, falling edges or any edge as the edge which triggers an input capture event. when the selected edge is detected, the interrupt ?g is set. the ?g is cleared by the two-step sequence described in section 16.6.2, ?escription of interrupt operation . 16.6.2.2.2 output compare events when a channel is con?ured as an output compare channel, the interrupt ?g is set each time the main timer counter matches the 16-bit value in the channel value register. the ?g is cleared by the two-step sequence described section 16.6.2, ?escription of interrupt operation . 16.6.2.2.3 pwm end-of-duty-cycle events for channels con?ured for pwm operation there are two possibilities. when the channel is con?ured for edge-aligned pwm, the channel ?g gets set when the timer counter matches the channel value register which marks the end of the active duty cycle period. when the channel is con?ured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel ?g is set at the start and at the end of the active duty cycle period which are the times when the timer counter matches the channel value register. the ?g is cleared by the two-step sequence described section 16.6.2, ?escription of interrupt operation . 16.7 the differences from tpm v2 to tpm v3 1. write to tpmxcnth:l registers ( section 16.3.2, ?pm-counter registers (tpmxcnth:tpmxcntl)) [se110-tpm case 7] any write to tpmxcnth or tpmxcntl registers in tpm v3 clears the tpm counter (tpmxcnth:l) and the prescaler counter. instead, in the tpm v2 only the tpm counter is cleared in this case. 2. read of tpmxcnth:l registers ( section 16.3.2, ?pm-counter registers (tpmxcnth:tpmxcntl)) in tpm v3, any read of tpmxcnth:l registers during bdm mode returns the value of the tpm counter that is frozen. in tpm v2, if only one byte of the tpmxcnth:l registers was read before the bdm mode became active, then any read of tpmxcnth:l registers during
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 342 freescale semiconductor bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the frozen tpm counter value. this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxsc, tpmxcnth or tpmxcntl. instead, in these conditions the tpm v2 does not clear this read coherency mechanism. 3. read of tpmxcnvh:l registers ( section 16.3.5, ?pm channel value registers (tpmxcnvh:tpmxcnvl)) in tpm v3, any read of tpmxcnvh:l registers during bdm mode returns the value of the tpmxcnvh:l register. in tpm v2, if only one byte of the tpmxcnvh:l registers was read before the bdm mode became active, then any read of tpmxcnvh:l registers during bdm mode returns the latched value of tpmxcnth:l from the read buffer instead of the value in the tpmxcnvh:l registers. this read coherency mechanism is cleared in tpm v3 in bdm mode if there is a write to tpmxcnsc. instead, in this condition the tpm v2 does not clear this read coherency mechanism. 4. write to tpmxcnvh:l registers input capture mode ( section 16.4.2.1, ?nput capture mode ) in this mode the tpm v3 does not allow the writes to tpmxcnvh:l registers. instead, the tpm v2 allows these writes. output compare mode ( section 16.4.2.2, ?utput compare mode ) in this mode and if (clksb:clksa not = 0:0), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer at the next change of the tpm counter (end of the prescaler counting) after the second byte is written. instead, the tpm v2 always updates these registers when their second byte is written. the following procedure can be used in the tpm v3 to verify if the tpmxcnvh:l registers were updated with the new value that was written to these registers (value in their write buffer). ... write the new value to tpmxcnvh:l; read tpmxcnvh and tpmxcnvl registers; while (the read value of tpmxcnvh:l is different from the new value written to tpmxcnvh:l) begin read again tpmxcnvh and tpmxcnvl; end ... in this point, the tpmxcnvh:l registers were updated, so the program can continue and, for example, write to tpmxc0sc without cancelling the previous write to tpmxcnvh:l registers. edge-aligned pwm ( section 16.4.2.3, ?dge-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes were written and when the
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 343 tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to $0000. center-aligned pwm ( section 16.4.2.4, ?enter-aligned pwm mode ) in this mode and if (clksb:clksa not = 00), the tpm v3 updates the tpmxcnvh:l registers with the value of their write buffer after that the both bytes were written and when the tpm counter changes from (tpmxmodh:l - 1) to (tpmxmodh:l). if the tpm counter is a free-running counter, then this update is made when the tpm counter changes from $fffe to $ffff. instead, the tpm v2 makes this update after that the both bytes were written and when the tpm counter changes from tpmxmodh:l to (tpmxmodh:l - 1). 5. center-aligned pwm ( section 16.4.2.4, ?enter-aligned pwm mode ) tpmxcnvh:l = tpmxmodh:l [se110-tpm case 1] in this case, the tpm v3 produces 100% duty cycle. instead, the tpm v2 produces 0% duty cycle. tpmxcnvh:l = (tpmxmodh:l - 1) [se110-tpm case 2] in this case, the tpm v3 produces almost 100% duty cycle. instead, the tpm v2 produces 0% duty cycle. tpmxcnvh:l is changed from 0x0000 to a non-zero value [se110-tpm case 3 and 5] in this case, the tpm v3 waits for the start of a new pwm period to begin using the new duty cycle setting. instead, the tpm v2 changes the channel output at the middle of the current pwm period (when the count reaches 0x0000). tpmxcnvh:l is changed from a non-zero value to 0x0000 [se110-tpm case 4] in this case, the tpm v3 ?ishes the current pwm period using the old duty cycle setting. instead, the tpm v2 ?ishes the current pwm period using the new duty cycle setting. 6. write to tpmxmodh:l registers in bdm mode ( section 16.3.3, ?pm counter modulo registers (tpmxmodh:tpmxmodl) ) in the tpm v3 a write to tpmxsc register in bdm mode clears the write coherency mechanism of tpmxmodh:l registers. instead, in the tpm v2 this coherency mechanism is not cleared when there is a write to tpmxsc register. 7. update of epwm signal when clksb:clksa = 00 in the tpm v3 if clksb:clksa = 00, then the epwm signal in the channel output is not update (it is frozen while clksb:clksa = 00). instead, in the tpm v2 the epwm signal is updated at the next rising edge of bus clock after a write to tpmxcnsc register. the figure 0-1 and figure 0-2 show when the epwm signals generated by tpm v2 and tpm v3 after the reset (clksb:clksa = 00) and if there is a write to tpmxcnsc register.
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 344 freescale semiconductor figure 0-1. generation of high-true epwm signal by tpm v2 and v3 after the reset figure 0-2. generation of low-true epwm signal by tpm v2 and v3 after the reset the following procedure can be used in tpm v3 (when the channel pin is also a port pin) to emulate the high-true epwm generated by tpm v2 after the reset. elsnb:elsna bits clksb:clksa bits 0 tpmxmodh:tpmxmodl = 0x0007 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmv2 tpmxchn epwm mode 00 00 10 bus clock 01 1234567 01 2 chnf bit msnb:msna bits 00 10 (in tpmv2 and tpmv3) tpmv3 tpmxchn ... reset (active low) elsnb:elsna bits clksb:clksa bits 0 tpmxmodh:tpmxmodl = 0x0007 tpmxcnvh:tpmxcnvl = 0x0005 tpmxcnth:tpmxcntl tpmv2 tpmxchn epwm mode 00 00 01 bus clock 01 1234567 01 2 chnf bit msnb:msna bits 00 10 (in tpmv2 and tpmv3) tpmv3 tpmxchn ... reset (active low)
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 345 ... con?ure the channel pin as output port pin and set the output pin; con?ure the channel to generate the epwm signal but keep elsnb:elsna as 00; con?ure the other registers (tpmxmodh, tpmxmodl, tpmxcnvh, tpmxcnvl, ...); con?ure clksb:clksa bits (tpm v3 starts to generate the high-true epwm signal, however tpm does not control the channel pin, so the epwm signal is not available); wait until the tof is set (or use the tof interrupt); enable the channel output by con?uring elsnb:elsna bits (now epwm signal is available); ...
chapter 16 timer/pwm module (s08tpmv3) mc9s08de60 series data sheet, rev. 3 346 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 347 chapter 17 development support 17.1 introduction development support systems in the hcs08 include the background debug controller (bdc) and the on-chip debug module (dbg). the bdc provides a single-wire debug interface to the target mcu that provides a convenient interface for programming the on-chip flash and other nonvolatile memories. the bdc is also the primary debug interface for development and allows non-intrusive access to memory data and traditional debug features such as cpu register modify, breakpoints, and single instruction trace commands. in the hcs08 family, address and data bus signals are not available on external pins (not even in test modes). debug is done through commands fed into the target mcu via the single-wire background debug interface. the debug module provides a means to selectively trigger and capture bus information so an external development system can reconstruct what happened inside the mcu on a cycle-by-cycle basis without having external access to the address and data signals. 17.1.1 forcing active background the method for forcing active background mode depends on the speci? hcs08 derivative. for the mc9s08de60, you can force active background after a power-on reset by holding the bkgd pin low as the device exits the reset condition. you can also force active background by driving bkgd low immediately after a serial background command that writes a one to the bdfr bit in the sbdfr register. if no debug pod is connected to the bkgd pin, the mcu will always reset into normal operating mode.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 348 freescale semiconductor 17.1.2 features features of the bdc module include: single pin for mode selection and background communications bdc registers are not located in the memory map sync command to determine target communications rate non-intrusive commands for memory access active background mode commands for cpu register access go and trace1 commands background command can wake cpu from stop or wait modes one hardware address breakpoint built into bdc oscillator runs in stop mode, if bdc enabled cop watchdog disabled while in active background mode features of the ice system include: two trigger comparators: two address + read/write (r/w) or one full address + data + r/w flexible 8-word by 16-bit fifo (?st-in, ?st-out) buffer for capture information: change-of-?w addresses or event-only data two types of breakpoints: tag breakpoints for instruction opcodes force breakpoints for any address access nine trigger modes: basic: a-only, a or b sequence: a then b full: a and b data, a and not b data event (store data): event-only b, a then event-only b range: inside range (a address b), outside range (address < a or address > b) 17.2 background debug controller (bdc) all mcus in the hcs08 family contain a single-wire background debug interface that supports in-circuit programming of on-chip nonvolatile memory and sophisticated non-intrusive debug capabilities. unlike debug interfaces on earlier 8-bit mcus, this system does not interfere with normal application resources. it does not use any user memory or locations in the memory map and does not share any on-chip peripherals. bdc commands are divided into two groups: active background mode commands require that the target mcu is in active background mode (the user program is not running). active background mode commands allow the cpu registers to be read or written, and allow the user to trace one user instruction at a time, or go to the user program from active background mode.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 349 non-intrusive commands can be executed at any time even while the users program is running. non-intrusive commands allow a user to read or write mcu memory locations or access status and control registers within the background debug controller. typically, a relatively simple interface pod is used to translate commands from a host computer into commands for the custom serial interface to the single-wire background debug system. depending on the development tool vendor, this interface pod may use a standard rs-232 serial port, a parallel printer port, or some other type of communications such as a universal serial bus (usb) to communicate between the host pc and the pod. the pod typically connects to the target system with ground, the bkgd pin, reset, and sometimes v dd . an open-drain connection to reset allows the host to force a target system reset, which is useful to regain control of a lost target system or to control startup of a target system before the on-chip nonvolatile memory has been programmed. sometimes v dd can be used to allow the pod to use power from the target system to avoid the need for a separate power supply. however, if the pod is powered separately, it can be connected to a running target system without forcing a target system reset or otherwise disturbing the running application program. figure 17-1. bdm tool connector 17.2.1 bkgd pin description bkgd is the single-wire background debug interface pin. the primary function of this pin is for bidirectional serial communication of active background mode commands and data. during reset, this pin is used to select between starting in active background mode or starting the users application program. this pin is also used to request a timed sync response pulse to allow a host development tool to determine the correct clock frequency for background debug serial communications. bdc serial communications use a custom serial protocol ?st introduced on the m68hc12 family of microcontrollers. this protocol assumes the host knows the communication clock rate that is determined by the target bdc clock rate. all communication is initiated and controlled by the host that drives a high-to-low edge to signal the beginning of each bit time. commands and data are sent most signi?ant bit ?st (msb ?st). for a detailed description of the communications protocol, refer to section 17.2.2, ?ommunication details. if a host is attempting to communicate with a target mcu that has an unknown bdc clock rate, a sync command may be sent to the target mcu to request a timed sync response signal from which the host can determine the correct communication speed. bkgd is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required. unlike typical open-drain pins, the external rc time constant on this pin, which is in?enced by external capacitance, plays almost no role in signal rise time. the custom protocol provides for brief, actively driven speedup pulses to force rapid rise times on this pin without risking harmful drive level con?cts. refer to section 17.2.2, ?ommunication details , for more detail. 2 4 6 no connect 5 no connect 3 1 reset bkgd gnd v dd
chapter 17 development support mc9s08de60 series data sheet, rev. 3 350 freescale semiconductor when no debugger pod is connected to the 6-pin bdm interface connector, the internal pullup on bkgd chooses normal operating mode. when a debug pod is connected to bkgd it is possible to force the mcu into active background mode after reset. the speci? conditions for forcing active background depend upon the hcs08 derivative (refer to the introduction to this development support section). it is not necessary to reset the target mcu to communicate with it through the background debug interface. 17.2.2 communication details the bdc serial interface requires the external controller to generate a falling edge on the bkgd pin to indicate the start of each bit time. the external controller provides this falling edge whether data is transmitted or received. bkgd is a pseudo-open-drain pin that can be driven either by an external controller or by the mcu. data is transferred msb ?st at 16 bdc clock cycles per bit (nominal speed). the interface times out if 512 bdc clock cycles occur between falling edges from the host. any bdc command that was in progress when this timeout occurs is aborted without affecting the memory or operating mode of the target mcu system. the custom serial protocol requires the debug pod to know the target bdc communication clock speed. the clock switch (clksw) control bit in the bdc status and control register allows the user to select the bdc clock source. the bdc clock source can either be the bus or the alternate bdc clock source. the bkgd pin can receive a high or low level or transmit a high or low level. the following diagrams show timing for each of these cases. interface timing is synchronous to clocks in the target bdc, but asynchronous to the external host. the internal bdc clock signal is shown for reference in counting cycles.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 351 figure 17-2 shows an external host transmitting a logic 1 or 0 to the bkgd pin of a target hcs08 mcu. the host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. ten target bdc clock cycles later, the target senses the bit level on the bkgd pin. typically, the host actively drives the pseudo-open-drain bkgd pin during host-to-target transmissions to speed up rising edges. because the target does not drive the bkgd pin during the host-to-target transmission period, there is no need to treat the line as an open-drain signal during this period. figure 17-2. bdc host-to-target serial bit timing earliest start target senses bit level 10 cycles synchronization uncertainty bdc clock (target mcu) host transmit 1 host transmit 0 perceived start of bit time of next bit
chapter 17 development support mc9s08de60 series data sheet, rev. 3 352 freescale semiconductor figure 17-3 shows the host receiving a logic 1 from the target hcs08 mcu. because the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the perceived start of the bit time in the target mcu. the host holds the bkgd pin low long enough for the target to recognize it (at least two target bdc cycles). the host must release the low drive before the target mcu drives a brief active-high speedup pulse seven cycles after the perceived start of the bit time. the host should sample the bit level about 10 cycles after it started the bit time. figure 17-3. bdc target-to-host serial bit timing (logic 1) host samples bkgd pin 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu speedup pulse perceived start of bit time high-impedance high-impedance high-impedance bkgd pin r-c rise 10 cycles earliest start of next bit
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 353 figure 17-4 shows the host receiving a logic 0 from the target hcs08 mcu. because the host is asynchronous to the target mcu, there is a 0-to-1 cycle delay from the host-generated falling edge on bkgd to the start of the bit time as perceived by the target mcu. the host initiates the bit time but the target hcs08 ?ishes it. because the target wants the host to receive a logic 0, it drives the bkgd pin low for 13 bdc clock cycles, then brie? drives it high to speed up the rising edge. the host samples the bit level about 10 cycles after starting the bit time. figure 17-4. bdm target-to-host serial bit timing (logic 0) 10 cycles bdc clock (target mcu) host drive to bkgd pin target mcu drive and perceived start of bit time high-impedance bkgd pin 10 cycles speed-up pulse speedup pulse earliest start of next bit host samples bkgd pin
chapter 17 development support mc9s08de60 series data sheet, rev. 3 354 freescale semiconductor 17.2.3 bdc commands bdc commands are sent serially from a host computer to the bkgd pin of the target hcs08 mcu. all commands and data are sent msb-?st using a custom bdc communications protocol. active background mode commands require that the target mcu is currently in the active background mode while non-intrusive commands may be issued at any time whether the target mcu is in active background mode or running a user application program. table 17-1 shows all hcs08 bdc commands, a shorthand description of their coding structure, and the meaning of each command. coding structure nomenclature this nomenclature is used in table 17-1 to describe the coding structure of the bdc commands. commands begin with an 8-bit hexadecimal command code in the host-to-target direction (most signi?ant bit ?st) / = separates parts of the command d = delay 16 target bdc clock cycles aaaa = a 16-bit address in the host-to-target direction rd = 8 bits of read data in the target-to-host direction wd = 8 bits of write data in the host-to-target direction rd16 = 16 bits of read data in the target-to-host direction wd16 = 16 bits of write data in the host-to-target direction ss = the contents of bdcscr in the target-to-host direction (status) cc = 8 bits of write data for bdcscr in the host-to-target direction (control) rbkp = 16 bits of read data in the target-to-host direction (from bdcbkpt breakpoint register) wbkp = 16 bits of write data in the host-to-target direction (for bdcbkpt breakpoint register)
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 355 table 17-1. bdc command summary command mnemonic active bdm/ non-intrusive coding structure description sync non-intrusive n/a 1 1 the sync command is a special operation that does not have a command code. request a timed reference pulse to determine target bdc communication speed ack_enable non-intrusive d5/d enable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. ack_disable non-intrusive d6/d disable acknowledge protocol. refer to freescale document order no. hcs08rmv1/d. background non-intrusive 90/d enter active background mode if enabled (ignore if enbdm bit equals 0) read_status non-intrusive e4/ss read bdc status from bdcscr write_control non-intrusive c4/cc write bdc controls in bdcscr read_byte non-intrusive e0/aaaa/d/rd read a byte from target memory read_byte_ws non-intrusive e1/aaaa/d/ss/rd read a byte and report status read_last non-intrusive e8/ss/rd re-read byte from address just read and report status write_byte non-intrusive c0/aaaa/wd/d write a byte to target memory write_byte_ws non-intrusive c1/aaaa/wd/d/ss write a byte and report status read_bkpt non-intrusive e2/rbkp read bdcbkpt breakpoint register write_bkpt non-intrusive c2/wbkp write bdcbkpt breakpoint register go active bdm 08/d go to execute the user application program starting at the address currently in the pc trace1 active bdm 10/d trace 1 user instruction at the address in the pc, then return to active background mode taggo active bdm 18/d same as go but enable external tagging (hcs08 devices have no external tagging pin) read_a active bdm 68/d/rd read accumulator (a) read_ccr active bdm 69/d/rd read condition code register (ccr) read_pc active bdm 6b/d/rd16 read program counter (pc) read_hx active bdm 6c/d/rd16 read h and x register pair (h:x) read_sp active bdm 6f/d/rd16 read stack pointer (sp) read_next active bdm 70/d/rd increment h:x by one then read memory byte located at h:x read_next_ws active bdm 71/d/ss/rd increment h:x by one then read memory byte located at h:x. report status and data. write_a active bdm 48/wd/d write accumulator (a) write_ccr active bdm 49/wd/d write condition code register (ccr) write_pc active bdm 4b/wd16/d write program counter (pc) write_hx active bdm 4c/wd16/d write h and x register pair (h:x) write_sp active bdm 4f/wd16/d write stack pointer (sp) write_next active bdm 50/wd/d increment h:x by one, then write memory byte located at h:x write_next_ws active bdm 51/wd/d/ss increment h:x by one, then write memory byte located at h:x. also report status.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 356 freescale semiconductor the sync command is unlike other bdc commands because the host does not necessarily know the correct communications speed to use for bdc communications until after it has analyzed the response to the sync command. to issue a sync command, the host: drives the bkgd pin low for at least 128 cycles of the slowest possible bdc clock (the slowest clock is normally the reference oscillator/64 or the self-clocked rate/64.) drives bkgd high for a brief speedup pulse to get a fast rise time (this speedup pulse is typically one cycle of the fastest clock in the system.) removes all drive to the bkgd pin so it reverts to high impedance monitors the bkgd pin for the sync response pulse the target, upon detecting the sync request from the host (which is a much longer low time than would ever occur during normal bdc communications): waits for bkgd to return to a logic high delays 16 cycles to allow the host to stop driving the high speedup pulse drives bkgd low for 128 bdc clock cycles drives a 1-cycle high speedup pulse to force a fast rise time on bkgd removes all drive to the bkgd pin so it reverts to high impedance the host measures the low time of this 128-cycle sync response pulse and determines the correct speed for subsequent bdc communications. typically, the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several percent. 17.2.4 bdc hardware breakpoint the bdc includes one relatively simple hardware breakpoint that compares the cpu address bus to a 16-bit match value in the bdcbkpt register. this breakpoint can generate a forced breakpoint or a tagged breakpoint. a forced breakpoint causes the cpu to enter active background mode at the ?st instruction boundary following any access to the breakpoint address. the tagged breakpoint causes the instruction opcode at the breakpoint address to be tagged so that the cpu will enter active background mode rather than executing that instruction if and when it reaches the end of the instruction queue. this implies that tagged breakpoints can only be placed at the address of an instruction opcode while forced breakpoints can be set at any address. the breakpoint enable (bkpten) control bit in the bdc status and control register (bdcscr) is used to enable the breakpoint logic (bkpten = 1). when bkpten = 0, its default value after reset, the breakpoint logic is disabled and no bdc breakpoints are requested regardless of the values in other bdc breakpoint registers and control bits. the force/tag select (fts) control bit in bdcscr is used to select forced (fts = 1) or tagged (fts = 0) type breakpoints. the on-chip debug module (dbg) includes circuitry for two additional hardware breakpoints that are more ?xible than the simple breakpoint in the bdc module.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 357 17.3 on-chip debug system (dbg) because hcs08 devices do not have external address and data buses, the most important functions of an in-circuit emulator have been built onto the chip with the mcu. the debug system consists of an 8-stage fifo that can store address or data bus information, and a ?xible trigger system to decide when to capture bus information and what information to capture. the system relies on the single-wire background debug system to access debug control registers and to read results out of the eight stage fifo. the debug module includes control and status registers that are accessible in the users memory map. these registers are located in the high register space to avoid using valuable direct page memory space. most of the debug modules functions are used during development, and user programs rarely access any of the control and status registers for the debug module. the one exception is that the debug system can provide the means to implement a form of rom patching. this topic is discussed in greater detail in section 17.3.6, ?ardware breakpoints . 17.3.1 comparators a and b two 16-bit comparators (a and b) can optionally be quali?d with the r/w signal and an opcode tracking circuit. separate control bits allow you to ignore r/w for each comparator. the opcode tracking circuitry optionally allows you to specify that a trigger will occur only if the opcode at the speci?d address is actually executed as opposed to only being read from memory into the instruction queue. the comparators are also capable of magnitude comparisons to support the inside range and outside range trigger modes. comparators are disabled temporarily during all bdc accesses. the a comparator is always associated with the 16-bit cpu address. the b comparator compares to the cpu address or the 8-bit cpu data bus, depending on the trigger mode selected. because the cpu data bus is separated into a read data bus and a write data bus, the rwaen and rwa control bits have an additional purpose, in full address plus data comparisons they are used to decide which of these buses to use in the comparator b data bus comparisons. if rwaen = 1 (enabled) and rwa = 0 (write), the cpus write data bus is used. otherwise, the cpus read data bus is used. the currently selected trigger mode determines what the debugger logic does when a comparator detects a quali?d match condition. a match can cause: generation of a breakpoint to the cpu storage of data bus values into the fifo starting to store change-of-?w addresses into the fifo (begin type trace) stopping the storage of change-of-?w addresses into the fifo (end type trace) 17.3.2 bus capture information and fifo operation the usual way to use the fifo is to setup the trigger mode and other control options, then arm the debugger. when the fifo has ?led or the debugger has stopped storing data into the fifo, you would read the information out of it in the order it was stored into the fifo. status bits indicate the number of words of valid information that are in the fifo as data is stored into it. if a trace run is manually halted by writing 0 to arm before the fifo is full (cnt = 1:0:0:0), the information is shifted by one position and
chapter 17 development support mc9s08de60 series data sheet, rev. 3 358 freescale semiconductor the host must perform ((8 cnt) 1) dummy reads of the fifo to advance it to the ?st signi?ant entry in the fifo. in most trigger modes, the information stored in the fifo consists of 16-bit change-of-?w addresses. in these cases, read dbgfh then dbgfl to get one coherent word of information out of the fifo. reading dbgfl (the low-order byte of the fifo data port) causes the fifo to shift so the next word of information is available at the fifo data port. in the event-only trigger modes (see section 17.3.5, ?rigger modes ), 8-bit data information is stored into the fifo. in these cases, the high-order half of the fifo (dbgfh) is not used and data is read out of the fifo by simply reading dbgfl. each time dbgfl is read, the fifo is shifted so the next data value is available through the fifo data port at dbgfl. in trigger modes where the fifo is storing change-of-?w addresses, there is a delay between cpu addresses and the input side of the fifo. because of this delay, if the trigger event itself is a change-of-?w address or a change-of-?w address appears during the next two bus cycles after a trigger event starts the fifo, it will not be saved into the fifo. in the case of an end-trace, if the trigger event is a change-of-?w, it will be saved as the last change-of-?w entry for that debug run. the fifo can also be used to generate a pro?e of executed instruction addresses when the debugger is not armed. when arm = 0, reading dbgfl causes the address of the most-recently fetched opcode to be saved in the fifo. to use the pro?ing feature, a host debugger would read addresses out of the fifo by reading dbgfh then dbgfl at regular periodic intervals. the ?st eight values would be discarded because they correspond to the eight dbgfl reads needed to initially ?l the fifo. additional periodic reads of dbgfh and dbgfl return delayed information about executed instructions so the host debugger can develop a pro?e of executed instruction addresses. 17.3.3 change-of-flow information to minimize the amount of information stored in the fifo, only information related to instructions that cause a change to the normal sequential execution of instructions is stored. with knowledge of the source and object code program stored in the target system, an external debugger system can reconstruct the path of execution through many instructions from the change-of-?w information stored in the fifo. for conditional branch instructions where the branch is taken (branch condition was true), the source address is stored (the address of the conditional branch opcode). because bra and brn instructions are not conditional, these events do not cause change-of-?w information to be stored in the fifo. indirect jmp and jsr instructions use the current contents of the h:x index register pair to determine the destination address, so the debug system stores the run-time destination address for any indirect jmp or jsr. for interrupts, rti, or rts, the destination address is stored in the fifo as change-of-?w information. 17.3.4 tag vs. force breakpoints and triggers tagging is a term that refers to identifying an instruction opcode as it is fetched into the instruction queue, but not taking any other action until and unless that instruction is actually executed by the cpu. this distinction is important because any change-of-?w from a jump, branch, subroutine call, or interrupt causes some instructions that have been fetched into the instruction queue to be thrown away without being executed.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 359 a force-type breakpoint waits for the current instruction to ?ish and then acts upon the breakpoint request. the usual action in response to a breakpoint is to go to active background mode rather than continuing to the next instruction in the user application program. the tag vs. force terminology is used in two contexts within the debug module. the ?st context refers to breakpoint requests from the debug module to the cpu. the second refers to match signals from the comparators to the debugger control logic. when a tag-type break request is sent to the cpu, a signal is entered into the instruction queue along with the opcode so that if/when this opcode ever executes, the cpu will effectively replace the tagged opcode with a bgnd opcode so the cpu goes to active background mode rather than executing the tagged instruction. when the trgsel control bit in the dbgt register is set to select tag-type operation, the output from comparator a or b is quali?d by a block of logic in the debug module that tracks opcodes and only produces a trigger to the debugger if the opcode at the compare address is actually executed. there is separate opcode tracking logic for each comparator so more than one compare event can be tracked through the instruction queue at a time. 17.3.5 trigger modes the trigger mode controls the overall behavior of a debug run. the 4-bit trg ?ld in the dbgt register selects one of nine trigger modes. when trgsel = 1 in the dbgt register, the output of the comparator must propagate through an opcode tracking circuit before triggering fifo actions. the begin bit in dbgt chooses whether the fifo begins storing data when the quali?d trigger is detected (begin trace), or the fifo stores data in a circular fashion from the time it is armed until the quali?d trigger is detected (end trigger). a debug run is started by writing a 1 to the arm bit in the dbgc register, which sets the armf ?g and clears the af and bf ?gs and the cnt bits in dbgs. a begin-trace debug run ends when the fifo gets full. an end-trace run ends when the selected trigger event occurs. any debug run can be stopped manually by writing a 0 to arm or dbgen in dbgc. in all trigger modes except event-only modes, the fifo stores change-of-?w addresses. in event-only trigger modes, the fifo stores data in the low-order eight bits of the fifo. the begin control bit is ignored in event-only trigger modes and all such debug runs are begin type traces. when trgsel = 1 to select opcode fetch triggers, it is not necessary to use r/w in comparisons because opcode tags would only apply to opcode fetches that are always read cycles. it would also be unusual to specify trgsel = 1 while using a full mode trigger because the opcode value is normally known at a particular address. the following trigger mode descriptions only state the primary comparator conditions that lead to a trigger. either comparator can usually be further quali?d with r/w by setting rwaen (rwben) and the corresponding rwa (rwb) value to be matched against r/w. the signal from the comparator with optional r/w quali?ation is used to request a cpu breakpoint if brken = 1 and tag determines whether the cpu request will be a tag request or a force request.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 360 freescale semiconductor a-only ?trigger when the address matches the value in comparator a a or b ?trigger when the address matches either the value in comparator a or the value in comparator b a then b ?trigger when the address matches the value in comparator b but only after the address for another cycle matched the value in comparator a. there can be any number of cycles after the a match and before the b match. a and b data (full mode) ?this is called a full mode because address, data, and r/w (optionally) must match within the same bus cycle to cause a trigger event. comparator a checks address, the low byte of comparator b checks data, and r/w is checked against rwa if rwaen = 1. the high-order half of comparator b is not used. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the purpose of issuing the tag request to the cpu and the cpu breakpoint is issued when the comparator a address matches. a and not b data (full mode) ?address must match comparator a, data must not match the low half of comparator b, and r/w must match rwa if rwaen = 1. all three conditions must be met within the same bus cycle to cause a trigger. in full trigger modes it is not useful to specify a tag-type cpu breakpoint (brken = tag = 1), but if you do, the comparator b data match is ignored for the purpose of issuing the tag request to the cpu and the cpu breakpoint is issued when the comparator a address matches. event-only b (store data) ?trigger events occur each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. a then event-only b (store data) after the address has matched the value in comparator a, a trigger event occurs each time the address matches the value in comparator b. trigger events cause the data to be captured into the fifo. the debug run ends when the fifo becomes full. inside range (a address b) a trigger occurs when the address is greater than or equal to the value in comparator a and less than or equal to the value in comparator b at the same time. outside range (address < a or address > b) ?a trigger occurs when the address is either less than the value in comparator a or greater than the value in comparator b.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 361 17.3.6 hardware breakpoints the brken control bit in the dbgc register may be set to 1 to allow any of the trigger conditions described in section 17.3.5, ?rigger modes , to be used to generate a hardware breakpoint request to the cpu. tag in dbgc controls whether the breakpoint request will be treated as a tag-type breakpoint or a force-type breakpoint. a tag breakpoint causes the current opcode to be marked as it enters the instruction queue. if a tagged opcode reaches the end of the pipe, the cpu executes a bgnd instruction to go to active background mode rather than executing the tagged opcode. a force-type breakpoint causes the cpu to ?ish the current instruction and then go to active background mode. if the background mode has not been enabled (enbdm = 1) by a serial write_control command through the bkgd pin, the cpu will execute an swi instruction instead of going to active background mode. 17.4 register de?ition this section contains the descriptions of the bdc and dbg registers and control bits. refer to the high-page register summary in the device overview chapter of this data sheet for the absolute address assignments for all dbg registers. this section refers to registers and control bits only by their names. a freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. 17.4.1 bdc registers and control bits the bdc has two registers: the bdc status and control register (bdcscr) is an 8-bit register containing control and status bits for the background debug controller. the bdc breakpoint match register (bdcbkpt) holds a 16-bit breakpoint match address. these registers are accessed with dedicated serial bdc commands and are not located in the memory space of the target mcu (so they do not have addresses and cannot be accessed by user programs). some of the bits in the bdcscr have write limitations; otherwise, these registers may be read or written at any time. for example, the enbdm control bit may not be written while the mcu is in active background mode. (this prevents the ambiguous condition of the control bit forbidding active background mode while the mcu is already in active background mode.) also, the four status bits (bdmact, ws, wsf, and dvf) are read-only status indicators and can never be written by the write_control serial bdc command. the clock switch (clksw) control bit may be read or written at any time.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 362 freescale semiconductor 17.4.1.1 bdc status and control register (bdcscr) this register can be read or written by serial bdc commands (read_status and write_control) but is not accessible to user programs because it is not located in the normal memory map of the mcu. 76543210 r enbdm bdmact bkpten fts clksw ws wsf dvf w normal reset 00000000 reset in active bdm: 11001000 = unimplemented or reserved figure 17-5. bdc status and control register (bdcscr) table 17-2. bdcscr register field descriptions field description 7 enbdm enable bdm (permit active background mode) ?typically, this bit is written to 1 by the debug host shortly after the beginning of a debug session or whenever the debug host resets the target and remains 1 until a normal reset clears it. 0 bdm cannot be made active (non-intrusive commands still allowed) 1 bdm can be made active to allow active background mode commands 6 bdmact background mode active status ?this is a read-only status bit. 0 bdm not active (user application program running) 1 bdm active and waiting for serial commands 5 bkpten bdc breakpoint enable ?if this bit is clear, the bdc breakpoint is disabled and the fts (force tag select) control bit and bdcbkpt match register are ignored. 0 bdc breakpoint disabled 1 bdc breakpoint enabled 4 fts force/tag select ?when fts = 1, a breakpoint is requested whenever the cpu address bus matches the bdcbkpt match register. when fts = 0, a match between the cpu address bus and the bdcbkpt register causes the fetched opcode to be tagged. if this tagged opcode ever reaches the end of the instruction queue, the cpu enters active background mode rather than executing the tagged opcode. 0 tag opcode at breakpoint address and enter active background mode if cpu attempts to execute that instruction 1 breakpoint match forces active background mode at next instruction boundary (address need not be an opcode) 3 clksw select source for bdc communications clock ?clksw defaults to 0, which selects the alternate bdc clock source. 0 alternate bdc clock source 1 mcu bus clock
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 363 17.4.1.2 bdc breakpoint match register (bdcbkpt) this 16-bit register holds the address for the hardware breakpoint in the bdc. the bkpten and fts control bits in bdcscr are used to enable and con?ure the breakpoint logic. dedicated serial bdc commands (read_bkpt and write_bkpt) are used to read and write the bdcbkpt register but is not accessible to user programs because it is not located in the normal memory map of the mcu. breakpoints are normally set while the target mcu is in active background mode before running the user application program. for additional information about setup and use of the hardware breakpoint logic in the bdc, refer to section 17.2.4, ?dc hardware breakpoint . 17.4.2 system background debug force reset register (sbdfr) this register contains a single write-only control bit. a serial background mode command such as write_byte must be used to write to sbdfr. attempts to write this register from a user program are ignored. reads always return 0x00. 2 ws wait or stop status ?when the target cpu is in wait or stop mode, most bdc commands cannot function. however, the background command can be used to force the target cpu out of wait or stop and into active background mode where all bdc commands work. whenever the host forces the target mcu into active background mode, the host should issue a read_status command to check that bdmact = 1 before attempting other bdc commands. 0 target cpu is running user application code or in active background mode (was not in wait or stop mode when background became active) 1 target cpu is in wait or stop mode, or a background command was used to change from wait or stop to active background mode 1 wsf wait or stop failure status this status bit is set if a memory access command failed due to the target cpu executing a wait or stop instruction at or about the same time. the usual recovery strategy is to issue a background command to get out of wait or stop mode into active background mode, repeat the command that failed, then return to the user program. (typically, the host would restore cpu registers and stack values and re-execute the wait or stop instruction.) 0 memory access did not con?ct with a wait or stop instruction 1 memory access command failed because the cpu entered wait or stop mode 0 dvf data valid failure status ?this status bit is not used in the mc9s08de60 series because it does not have any slow access memory. 0 memory access did not con?ct with a slow memory access 1 memory access command failed because cpu was not ?ished with a slow memory access table 17-2. bdcscr register field descriptions (continued) field description
chapter 17 development support mc9s08de60 series data sheet, rev. 3 364 freescale semiconductor figure 17-6. system background debug force reset register (sbdfr) 17.4.3 dbg registers and control bits the debug module includes nine bytes of register space for three 16-bit registers and three 8-bit control and status registers. these registers are located in the high register space of the normal memory map so they are accessible to normal application programs. these registers are rarely if ever accessed by normal user application programs with the possible exception of a rom patching mechanism that uses the breakpoint logic. 17.4.3.1 debug comparator a high register (dbgcah) this register contains compare value bits for the high-order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.2 debug comparator a low register (dbgcal) this register contains compare value bits for the low-order eight bits of comparator a. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.3 debug comparator b high register (dbgcbh) this register contains compare value bits for the high-order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 17.4.3.4 debug comparator b low register (dbgcbl) this register contains compare value bits for the low-order eight bits of comparator b. this register is forced to 0x00 at reset and can be read at any time or written at any time unless arm = 1. 76543210 r00000000 w bdfr 1 1 bdfr is writable only through serial background mode debug commands, not from user programs. reset 00000000 = unimplemented or reserved table 17-3. sbdfr register field description field description 0 bdfr background debug force reset a serial active background mode command such as write_byte allows an external debug host to force a target system reset. writing 1 to this bit forces an mcu reset. this bit cannot be written from a user program.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 365 17.4.3.5 debug fifo high register (dbgfh) this register provides read-only access to the high-order eight bits of the fifo. writes to this register have no meaning or effect. in the event-only trigger modes, the fifo only stores data into the low-order byte of each fifo word, so this register is not used and will read 0x00. reading dbgfh does not cause the fifo to shift to the next word. when reading 16-bit words out of the fifo, read dbgfh before reading dbgfl because reading dbgfl causes the fifo to advance to the next word of information. 17.4.3.6 debug fifo low register (dbgfl) this register provides read-only access to the low-order eight bits of the fifo. writes to this register have no meaning or effect. reading dbgfl causes the fifo to shift to the next available word of information. when the debug module is operating in event-only modes, only 8-bit data is stored into the fifo (high-order half of each fifo word is unused). when reading 8-bit words out of the fifo, simply read dbgfl repeatedly to get successive bytes of data from the fifo. it isnt necessary to read dbgfh in this case. do not attempt to read data from the fifo while it is still armed (after arming but before the fifo is ?led or armf is cleared) because the fifo is prevented from advancing during reads of dbgfl. this can interfere with normal sequencing of reads from the fifo. reading dbgfl while the debugger is not armed causes the address of the most-recently fetched opcode to be stored to the last location in the fifo. by reading dbgfh then dbgfl periodically, external host software can develop a pro?e of program execution. after eight reads from the fifo, the ninth read will return the information that was stored as a result of the ?st read. to use the pro?ing feature, read the fifo eight times without using the data to prime the sequence and then begin using the data to get a delayed picture of what addresses were being executed. the information stored into the fifo on reads of dbgfl (while the fifo is not armed) is the address of the most-recently fetched opcode.
chapter 17 development support mc9s08de60 series data sheet, rev. 3 366 freescale semiconductor 17.4.3.7 debug control register (dbgc) this register can be read or written at any time. 76543210 r dbgen arm tag brken rwa rwaen rwb rwben w reset 00000000 figure 17-7. debug control register (dbgc) table 17-4. dbgc register field descriptions field description 7 dbgen debug module enable ?used to enable the debug module. dbgen cannot be set to 1 if the mcu is secure. 0 dbg disabled 1 dbg enabled 6 arm arm control controls whether the debugger is comparing and storing information in the fifo. a write is used to set this bit (and armf) and completion of a debug run automatically clears it. any debug run can be manually stopped by writing 0 to arm or to dbgen. 0 debugger not armed 1 debugger armed 5 tag tag/force select ?controls whether break requests to the cpu will be tag or force type requests. if brken = 0, this bit has no meaning or effect. 0 cpu breaks requested as force type requests 1 cpu breaks requested as tag type requests 4 brken break enable controls whether a trigger event will generate a break request to the cpu. trigger events can cause information to be stored in the fifo without generating a break request to the cpu. for an end trace, cpu break requests are issued to the cpu when the comparator(s) and r/w meet the trigger requirements. for a begin trace, cpu break requests are issued when the fifo becomes full. trgsel does not affect the timing of cpu break requests. 0 cpu break requests not enabled 1 triggers cause a break request to the cpu 3 rwa r/w comparison value for comparator a when rwaen = 1, this bit determines whether a read or a write access quali?s comparator a. when rwaen = 0, rwa and the r/w signal do not affect comparator a. 0 comparator a can only match on a write cycle 1 comparator a can only match on a read cycle 2 rwaen enable r/w for comparator a ?controls whether the level of r/w is considered for a comparator a match. 0 r/w is not used in comparison a 1 r/w is used in comparison a 1 rwb r/w comparison value for comparator b when rwben = 1, this bit determines whether a read or a write access quali?s comparator b. when rwben = 0, rwb and the r/w signal do not affect comparator b. 0 comparator b can match only on a write cycle 1 comparator b can match only on a read cycle 0 rwben enable r/w for comparator b ?controls whether the level of r/w is considered for a comparator b match. 0 r/w is not used in comparison b 1 r/w is used in comparison b
chapter 17 development support mc9s08de60 series data sheet, rev. 3 freescale semiconductor 367 17.4.3.8 debug trigger register (dbgt) this register can be read any time, but may be written only if arm = 0, except bits 4 and 5 are hard-wired to 0s. 76543210 r trgsel begin 00 trg3 trg2 trg1 trg0 w reset 00000000 = unimplemented or reserved figure 17-8. debug trigger register (dbgt) table 17-5. dbgt register field descriptions field description 7 trgsel trigger type ?controls whether the match outputs from comparators a and b are quali?d with the opcode tracking logic in the debug module. if trgsel is set, a match signal from comparator a or b must propagate through the opcode tracking logic and a trigger event is only signalled to the fifo logic if the opcode at the match address is actually executed. 0 trigger on access to compare address (force) 1 trigger if opcode at compare address is executed (tag) 6 begin begin/end trigger select controls whether the fifo starts ?ling at a trigger or ?ls in a circular manner until a trigger ends the capture of information. in event-only trigger modes, this bit is ignored and all debug runs are assumed to be begin traces. 0 data stored in fifo until trigger (end trace) 1 trigger initiates data storage (begin trace) 3:0 trg[3:0] select trigger mode ?selects one of nine triggering modes, as described below. 0000 a-only 0001 a or b 0010 a then b 0011 event-only b (store data) 0100 a then event-only b (store data) 0101 a and b data (full mode) 0110 a and not b data (full mode) 0111 inside range: a address b 1000 outside range: address < a or address > b 1001 ?1111 (no trigger)
chapter 17 development support mc9s08de60 series data sheet, rev. 3 368 freescale semiconductor 17.4.3.9 debug status register (dbgs) this is a read-only status register. 76543210 r af bf armf 0 cnt3 cnt2 cnt1 cnt0 w reset 00000000 = unimplemented or reserved figure 17-9. debug status register (dbgs) table 17-6. dbgs register field descriptions field description 7 af trigger match a flag ?af is cleared at the start of a debug run and indicates whether a trigger match a condition was met since arming. 0 comparator a has not matched 1 comparator a match 6 bf trigger match b flag ?bf is cleared at the start of a debug run and indicates whether a trigger match b condition was met since arming. 0 comparator b has not matched 1 comparator b match 5 armf arm flag while dbgen = 1, this status bit is a read-only image of arm in dbgc. this bit is set by writing 1 to the arm control bit in dbgc (while dbgen = 1) and is automatically cleared at the end of a debug run. a debug run is completed when the fifo is full (begin trace) or when a trigger event is detected (end trace). a debug run can also be ended manually by writing 0 to arm or dbgen in dbgc. 0 debugger not armed 1 debugger armed 3:0 cnt[3:0] fifo valid count these bits are cleared at the start of a debug run and indicate the number of words of valid data in the fifo at the end of a debug run. the value in cnt does not decrement as data is read out of the fifo. the external debug host is responsible for keeping track of the count as information is read out of the fifo. 0000 number of valid words in fifo = no valid data 0001 number of valid words in fifo = 1 0010 number of valid words in fifo = 2 0011 number of valid words in fifo = 3 0100 number of valid words in fifo = 4 0101 number of valid words in fifo = 5 0110 number of valid words in fifo = 6 0111 number of valid words in fifo = 7 1000 number of valid words in fifo = 8
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 369 appendix a electrical characteristics a.1 introduction this section contains the most accurate electrical and timing information for the mc9s08de60 series of microcontrollers available at the time of publication. a.2 parameter classi?ation the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following classi?ation is used and the parameters are tagged accordingly in the tables where appropriate: note the classi?ation is shown in the column labeled ??in the parameter tables where appropriate. a.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits speci?d in table a-2 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. table a-1. parameter classi?ations p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 370 freescale semiconductor this device contains circuitry protecting against damage due to high static voltage or electrical ?lds; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ). a.4 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than being controlled by the mcu design. in order to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table a-2. absolute maximum ratings num rating symbol value unit 1 supply voltage v dd 0.3 to + 5.8 v 2 input voltage v in ?0.3 to v dd + 0.3 v 3 instantaneous maximum current single pin limit (applies to all port pins) 1, 2, 3 1 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low which would reduce overall power consumption. i d 25 ma 4 maximum current into v dd i dd 120 ma 5 storage temperature t stg 55 to +150 c
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 371 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. a-1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ?chip internal power p i/o = power dissipation on input and output pins ?user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273c) eqn. a-2 solving equations 1 and 2 for k gives: k = p d (t a + 273c) + ja (p d ) 2 eqn. a-3 where k is a constant pertaining to the particular part. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations 1 and 2 iteratively for any value of t a . table a-3. thermal characteristics num c rating symbol value unit temp. code 1d operating temperature range (packaged) t a ?0 to 125 ?0 to 105 ?0 to 85 c m v c 2t maximum junction temperature 1 1 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air ?w, power dissipation of other components on the board, and board thermal resistance. t j 135 c 3d thermal resistance 2 2 junction to ambient natural convection single-layer board 64-pin lqfp ja 69 c/w four-layer board 64-pin lqfp ja 51 c/w
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 372 freescale semiconductor a.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices than on early cmos circuits, normal handling precautions should be used to avoid exposure to static discharge. quali?ation tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test quali?ation for automotive grade integrated circuits. during the device qualification esd stresses were performed for the human body model (hbm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification. complete dc parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. table a-4. esd and latch-up test conditions model description symbol value unit human body series resistance r1 1500 storage capacitance c 100 pf number of pulse per pin 3 latch-up minimum input voltage limit ?.5 v maximum input voltage limit 7.5 v table a-5. esd and latch-up protection characteristics num rating symbol min max unit 1 human body model (hbm) v hbm +/- 2000 v 2 charge device model (cdm) v cdm +/- 500 v 3 latch-up current at t a = 125ci lat +/- 100 ma
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 373 a.6 dc characteristics this section includes information about power supply requirements, i/o pin characteristics, and power supply current in various operating modes. table a-6. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage v dd 2.7 5.5 v p all i/o pins, low-drive strength 5 v, i load = ? ma v dd ?1.5 c 3 v, i load = ?.6 ma v dd ?1.5 c output high voltage 5 v, i load = ?.4 ma v dd ?0.8 2c v oh 3 v, i load = ?.24 ma v dd ?0.8 v p all i/o pins, high-drive strength 5 v, i load = ?0 ma v dd ?1.5 c 3 v, i load = ? ma v dd ?1.5 c 5 v, i load = ? ma v dd ?0.8 c 3 v, i load = ?.4 ma v dd ?0.8 3 c output high current max total i oh for all ports i oht 5 v 0 -100 ma 3 v 0 -60 p all i/o pins, low-drive strength 5 v, i load = 2 ma 1.5 c 3 v, i load = 0.6 ma 1.5 c output low voltage 5 v, i load = 0.4 ma 0.8 4c v ol 3 v, i load = 0.24 ma 0.8 v p all i/o pins, high-drive strength 5 v, i load = 10 ma 1.5 c 3 v, i load = 3 ma 1.5 c 5 v, i load = 2 ma 0.8 c 3 v, i load = 0.4 ma 0.8 5 c output low current max total i ol for all ports i olt 5 v 0 100 ma 3 v 0 60 6 c input high voltage; all digital inputs v ih 5v 0.65 x v dd v c input low voltage; all digital inputs v il 5v 0.35 x v dd 7 c input hysteresis v hys 0.06 x v dd mv 8 9p input leakage current (per pin) all input only pins | i in | v in = v dd or v ss 0.1 1 a 10 p hi-z (off-state) leakage current (per pin) all input/output | i oz | v in = v dd or v ss 0.1 1 a 11 p pullup resistors (or pulldown 2 resistors when enabled) r pu , r pd 5 v 20 45 65 k c3 v 2 0 4 5 6 5 12 t input capacitance, all pins c in 8pf 13 d ram retention voltage v ram 0.6 1.0 v
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 374 freescale semiconductor 14 d por re-arm voltage 3 v por 0.9 1.4 2.0 v 15 d por re-arm time 4 t por 10 s 16 p low-voltage detection threshold high range v dd falling v dd rising v lvd1 3.9 4.0 4.0 4.1 4.1 4.2 v p low-voltage detection threshold low range v dd falling v dd rising v lvd0 2.48 2.54 2.56 2.62 2.64 2.70 v 17 c low-voltage warning threshold high range 1 v dd falling v dd rising v lvw3 4.5 4.6 4.6 4.7 4.7 4.8 v 18 p low-voltage warning threshold high range 0 v dd falling v dd rising v lvw2 4.2 4.3 4.3 4.4 4.4 4.5 v 19 p low-voltage warning threshold low range 1 v dd falling v dd rising v lvw1 2.84 2.90 2.92 2.98 3.00 3.06 v 20 c low-voltage warning threshold low range 0 v dd falling v dd rising v lvw0 2.66 2.72 2.74 2.80 2.82 2.88 v 21 22 t low-voltage inhibit reset/recover hysteresis v hys 5 v 100 mv 3 v 60 23 dc injection current 5, 6, 7, 8 single pin limit v in > v dd 0? di ic v in < v ss 0 ?.2 ma total mcu limit, includes sum of all stressed pins v in > v dd 025 v in < v ss 05 24 c bandgap voltage reference factory trimmed at v dd = 5.0 v, temp = 25 c v bg 1.19 1.20 1.21 v 1 typical values are measured at 25 c. characterized, not tested 2 when a pin interrupt is con?ured to detect rising edges, pulldown resistors are used in place of pullup resistors. 3 maximum is highest voltage that por is guaranteed. 4 simulated, not tested 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in >v dd ) is greater than i dd , the injection current may ?w out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low which (would reduce overall power consumption). 6 all functional non-supply pins are internally clamped to v ss and v dd . table a-6. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 375 a.7 supply current characteristics 7 input must be current limited to the value speci?d. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. 8 pte1 does not have a clamp diode to v dd . do not drive pte1 above v dd . table a-7. supply current characteristics num c parameter symbol v dd (v) typical 1 max 2 unit 1c run supply current 3 measured at (cpu clock = 2 mhz, f bus = 1 mhz ecc off ri dd 5 3 7.5 ma 3 2.8 7.4 ecc on 5 3 7.5 3 2.8 7.4 2 p run supply current 3 measured at (cpu clock = 16 mhz, f bus = 8 mhz) ri dd 5 7.7 11.4 ma c 3 7.4 11.2 3 p run supply current 3 measured at (cpu clock = 40 mhz, f bus = 20 mhz) ri dd 515 24 ma c 3 14 23 4 p 4 stop3 mode supply current ?0 c (c, v, & m suf?) 0.9 p 4 25 c (all parts) 5 1.0 p 105 c (v suf? only) 26 39 p 125 c (m suf? only) s3i dd 62 90 a c ?0 c (c, v, & m suf?) 0.8 c25 c (all parts) 3 0.9 c 105 c (v suf? only) 21 32 c 125 c (m suf? only) 52 80
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 376 freescale semiconductor 5 p 4 stop2 mode supply current ?0 c (c, v, & m suf?) 0.8 p 4 25 c (all parts) 5 0.9 p 105 c (v suf? only) 25 37 p 125 c (m suf? only) s2i dd 46 70 a c ?0 c (c, v, & m suf?) 0.7 c25 c (all parts) 3 0.8 c 105 c (v suf? only) 20 30 c 125 c (m suf? only) 40 60 6c rtc adder to stop2 or stop3 5 , 25c 5 300 na 3 300 na 7c lvd adder to stop3 (lvde = lvdse = 1) 5 110 a 390 a 8c adder to stop3 for oscillator enabled 6 (irclken = 1 and irefsten = 1 or erclken = 1 and erefsten = 1) 55 a 35 a 1 typicals are measured at 25 c, unless otherwise noted. 2 maximum values in this column apply for the full operating temperature range of the device unless otherwise noted. 3 all modules except adc active, mcg con?ured for fbe, and does not include any dc loads on port pins 4 stop currents are tested in production for 25 c on all parts. tests at other temperatures depend upon the part number suf? and maturity of the product. freescale may eliminate a test insertion at a particular temperature from the production test ?w once suf?ient data has been collected and is approved. 5 most customers are expected to ?d that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait mode. 6 values given under the following conditions: low range operation (range = 0), low power mode (hgo = 0). table a-7. supply current characteristics (continued) num c parameter symbol v dd (v) typical 1 max 2 unit
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 377 a.8 analog comparator (acmp) electricals a.9 adc characteristics table a-8. analog comparator electrical speci?ations num c rating symbol min typical max unit 1 supply voltage v dd 2.7 5.5 v 2 d supply current (active) i ddac ?035 a 3 d analog input voltage v ain v ss ?0.3 v dd v 4 d analog input offset voltage v aio 20 40 mv 5d analog comparator hysteresis v h 3.0 6.0 20.0 mv 6 d analog input leakage current i alkg -- -- 1.0 a 7 d analog comparator initialization delay t ainit 1.0 s table a-9. 12-bit adc operating conditions characteristic conditions symb min typ 1 max unit comment supply voltage absolute v ddad 2.7 5.5 v delta to v dd (v dd -v ddad ) 2 v ddad -100 0 +100 mv ground voltage delta to v ss (v ss -v ssad ) 2 v ssad -100 0 +100 mv ref voltage high v refh 2.7 v ddad v ddad v applicable in only 64-pin packages {v refh < v ddad characterized but not production test} ref voltage low v refl v ssad v ssad v ssad v not applicable in 64-pin packages (only 32- and 48-pin packages) input voltage v adin v refl ? refh v input capacitance c adin 4.5 5.5 pf input resistance r adin ? 5k analog source resistance 12 bit mode f adck > 4mhz f adck < 4mhz r as 2 5 k external to mcu 10 bit mode f adck > 4mhz f adck < 4mhz 5 10 8 bit mode (all valid f adck )1 0
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 378 freescale semiconductor figure a-1. adc input impedance equivalency diagram adc conversion clock freq. high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0 1 typical values assume v ddad = 5.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 dc potential difference. table a-9. 12-bit adc operating conditions (continued) characteristic conditions symb min typ 1 max unit comment + + v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 379 table a-10. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic conditions c symb min typ 1 max unit comment supply current adlpc=1 adlsmp=1 adco=1 ti dd + i ddad 133 a adc current only supply current adlpc=1 adlsmp=0 adco=1 ti dd + i ddad 218 a adc current only supply current adlpc=0 adlsmp=1 adco=1 ti dd + i ddad 327 a adc current only supply current adlpc=0 adlsmp=0 adco=1 di dd + i ddad 0.582 1 ma adc current only supply current stop, reset, module off i dd + i ddad 0.011 1 a adc current only adc asynchronous clock source high speed (adlpc=0) p f adack 2 3.3 5 mhz t adack = 1/f adack low power (adlpc=1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp=0) d t adc 20 adck cycles see table 10-13 for conversion time variances long sample (adlsmp=1) 40 sample time short sample (adlsmp=0) d t ads 3.5 adck cycles long sample (adlsmp=1) 23.5 total unadjusted error 12 bit mode t e tue 3.0 10 lsb 2 includes quantization 10 bit mode p 1 2.5 8 bit mode t 0.5 1.0 differential non-linearity 12 bit mode t dnl 1.75 4.0 lsb 2 10 bit mode 3 p 0.5 1.0 8 bit mode 3 t 0.3 0.5 integral non-linearity 12 bit mode t inl 1.5 4.0 lsb 2 10 bit mode t 0.5 1.0 8 bit mode t 0.3 0.5 zero-scale error 12 bit mode t e zs 1.5 6.0 lsb 2 v adin = v ssad 10 bit mode p 0.5 1.5 8 bit mode t 0.5 0.5
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 380 freescale semiconductor full-scale error 12 bit mode t e fs 1 4.0 lsb 2 v adin =v ddad 10 bit mode t 0.5 1 8 bit mode t 0.5 0.5 quantization error 12 bit mode d e q -1 to 0 -1 to 0 lsb 2 10 bit mode 0.5 8 bit mode 0.5 input leakage error 12 bit mode d e il 1 10.0 lsb 2 pad leakage 4 * r as 10 bit mode 0.2 2.5 8 bit mode 0.1 1 temp sensor slope -40 c?25c d m 3.266 mv/ c 25c?125c 3.638 temp sensor voltage 25cd v temp25 1.396 v 1 typical values assume v ddad = 5.0v, temp = 25 c, f adck =1.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 1 lsb = (v refh - v refl )/2 n 3 monotonicity and no-missing-codes guaranteed in 10 bit and 8 bit modes 4 based on input pad leakage current. refer to pad electricals. table a-10. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions c symb min typ 1 max unit comment
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 381 a.10 external oscillator (xosc) characteristics table a-11. oscillator electrical speci?ations (temperature range = ?0 to 125 c ambient) num c rating symbol min typ 1 1 typical data was characterized at 3.0 v, 25 c or is recommended value. max unit 1 oscillator crystal or resonator (erefs = 1, erclken = 1 low range (range = 0) f lo 32 38.4 khz c high range (range = 1) fee or fbe mode 2 2 when mcg is configured for fee or fbe mode, the input clock source must be divisible using rdiv to within the range of 31.25 khz to 39.0625 khz. f hi-? 1 5 mhz high range (range = 1) pee or pbe mode 3 3 when mcg is con?ured for pee or pbe mode, input clock source must be divisible using rdiv to within the range of 1 mhz to 2 mhz. f hi-pll 1 16 mhz high range (range = 1, hgo = 1) blpe mode f hi-hgo 1 16 mhz high range (range = 1, hgo = 0) blpe mode f hi-lp 1 8 mhz 2 load capacitors c 1 c 2 see crystal or resonator manufacturer? recommendation. 3 feedback resistor low range (32 khz to 100 khz) r f ?0m high range (1 mhz to 16 mhz) 1 m 4 series resistor low range, low gain (range = 0, hgo = 0) 0 low range, high gain (range = 0, hgo = 1) 100 high range, low gain (range = 1, hgo = 0) r s ?k high range, high gain (range = 1, hgo = 1) 8 mhz 0 0 4 mhz 0 10 1 mhz 0 20 5 crystal start-up time 4 4 this parameter is characterized and not tested on each device. proper pc board layout procedures must be followed to achieve speci?ations. this data will vary based upon the crystal manufacturer and board design. the crystal should be characterized by the crystal manufacturer. low range, low gain (range = 0, hgo = 0) t cstl-lp 200 t low range, high gain (range = 0, hgo = 1) t cstl-hgo 400 high range, low gain (range = 1, hgo = 0) 5 5 4 mhz crystal. t csth-lp ?ms high range, high gain (range = 1, hgo = 1) 4 t csth-hgo ?5 6 square wave input clock frequency (erefs = 0, erclken = 1) t fee or fbe mode 2 0.03125 5 pee or pbe mode 3 f extal 1 16 mhz blpe mode 0 40
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 382 freescale semiconductor a.11 mcg speci?ations table a-12. mcg frequency speci?ations (temperature range = ?0 to 125 c ambient) num c rating symbol min typical max unit 1p internal reference frequency - factory trimmed at v dd = 5 v and temperature = 25 c f int_ft 31.25 khz 2p average internal reference frequency - untrimmed 1 f int_ut 25 32.7 41.66 khz 3p average internal reference frequency - user trimmed f int_t 31.25 39.0625 khz 4 d internal reference startup time t irefst 60 100 us 5 dco output frequency range - untrimmed 1 value provided for reference: f dco_ut = 1024 x f int_ut f dco_ut 25.6 33.48 42.66 mhz 6 p dco output frequency range - trimmed f dco_t 32 40 mhz 7c resolution of trimmed dco output frequency at ?ed voltage and temperature (using ftrim) f dco_res_t 0.1 0.2 %f dco 8c resolution of trimmed dco output frequency at ?ed voltage and temperature (not using ftrim) f dco_res_t 0.2 0.4 %f dco 9p total deviation of trimmed dco output frequency over voltage and temperature f dco_t + 0.5 -1.0 2 %f dco 10 c total deviation of trimmed dco output frequency over ?ed voltage and temperature range of 0-70 c f dco_t 0.5 1 %f dco 11 c fll acquisition time 2 t ?_acquire 1ms 12 d pll acquisition time 3 t pll_acquire 1ms 13 c long term jitter of dco output clock (averaged over 2ms interval) 4 c jitter 0.02 0.2 %f dco 14 d vco operating frequency f vco 7.0 55.0 mhz 15 d pll reference frequency range f pll_ref 1.0 2.0 mhz 16 t rms frequency variation of a single clock cycle measured 2 ms after reference edge. 5 f pll_cycjit_2ms 0.590 4 %f pll 17 t maximum frequency variation averaged over 2 ms window. f pll_maxjit_2ms 0.001 %f pll mcu extal xtal crystal or resonator r s c 2 r f c 1
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 383 18 t rms frequency variation of a single clock cycle measured 625 ns after reference edge. 6 f pll_cycjit_625ns 0.566 4 %f pll 19 t maximum frequency variation averaged over 625 ns window. f pll_maxjit_625ns 0.113 %f pll 20 d lock entry frequency tolerance 7 d lock 1.49 2.98 % 21 d lock exit frequency tolerance 8 d unl 4.47 5.97 % 22 d lock time - fll t ?_lock t ?_acquire+ 1075(1/ f int_t) s 23 d lock time - pll t pll_lock t pll_acquire+ 1075(1/ f pll_ref) s 24 d loss of external clock minimum frequency - range = 0 f loc_low (3/5) x f int khz 25 d loss of external clock minimum frequency - range = 1 f loc_high (16/5) x f int khz 1 trim register at default value (0x80) and ftrim control bit at default value (0x0). 2 this speci?ation applies to any time the fll reference source or reference divider is changed, trim value changed or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this speci?ation assumes it is already running. 3 this speci?ation applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this speci?ation assumes it is already running. 4 jitter is the average deviation from the programmed frequency measured over the speci?d interval at maximum f bus . measurements are made with the device powered by ?tered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. jitter measurements are based upon a 40mhz mcgout clock frequency. 5 in some speci?ations, this value is described as ?ong term accuracy of pll output clock (averaged over 2 ms) with symbol ? pll_jitter_2ms .?the parameter is unchanged, but the description has been changed for clari?ation purposes. 6 in some speci?ations, this value is described as ?itter of pll output clock measured over 625 ns?with symbol ? pll_jitter_625ns .?the parameter is unchanged, but the description has been changed for clari?ation purposes. 7 below d lock minimum, the mcg is guaranteed to enter lock. above d lock maximum, the mcg will not enter lock. but if the mcg is already in lock, then the mcg may stay in lock. 8 below d unl minimum, the mcg will not exit lock if already in lock. above d unl maximum, the mcg is guaranteed to exit lock. table a-12. mcg frequency speci?ations (temperature range = ?0 to 125 c ambient) (continued) num c rating symbol min typical max unit
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 384 freescale semiconductor a.12 ac characteristics this section describes ac timing characteristics for each peripheral system. a.12.1 control timing figure a-2. reset timing table a-13. control timing nu m c rating symbol min typical 1 1 typical data was characterized at 5.0 v, 25 c unless otherwise stated. max unit 1 d/ p bus frequency (t cyc = 1/f bus )f bus dc 20 mhz 2 t internal low-power oscillator period t lpo 1500 s 3d external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. shorter pulses are not guaranteed to override reset requests from internal sources. t extrst 1.5 x t cyc ?s 4d reset low drive 3 3 when any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of t cyc . after por reset, the bus clock frequency changes to the untrimmed dco frequency (freset = (f dco_ut )/4) because trim is reset to 0x80 and ftrim is reset to 0; and there is an extra divide-by-two because bdiv is reset to 0:1. after other resets, trim stays at the pre-reset value. t rstdrv 34 x t cyc ?s 5 d active background debug mode latch setup time t mssu 25 ns 6 d active background debug mode latch hold time t msh 25 ns 7d irq/piax/ pibx/pidx pulse width asynchronous path 2 synchronous path 3 t ilih, t ihil 100 1.5 t cyc ns 8t port rise and fall time low output drive (ptxds = 0) (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 4 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?0 c to 125c. t rise , t fall 40 75 ns port rise and fall time high output drive (ptxds = 1) (load = 50 pf) 4 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall 11 35 ns t extrst reset pin
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 385 figure a-3. active background debug mode latch timing figure a-4. pin interrupt timing a.12.2 timer/pwm synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. table a-14. tpm input timing num c rating symbol min max unit 1 external clock frequency f tclk dc f bus /4 mhz 2 external clock period t tclk 4 t cyc 3 d external clock high time t clkh 1.5 t cyc 4 d external clock low time t clkl 1.5 t cyc 5 d input capture pulse width t icpw 1.5 t cyc bkgd/ms reset t mssu t msh t ihil piax/pibx/pidx t ilih irq/piax/pibx/pidx
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 386 freescale semiconductor figure a-5. timer external clock figure a-6. timer input capture pulse a.12.3 mscan table a-15. mscan wake-up pulse characteristics num c rating symbol min typ max unit 1 d mscan wake-up dominant pulse ?tered t wup 2 s 2 d mscan wake-up dominant pulse pass t wup 5 s t tclk t clkh t clkl tpmxchn t icpw tpmxchn t icpw tpmxchn
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 387 a.12.4 spi table a-16 and figure a-7 through figure a-10 describe the timing requirements for the spi system. table a-16. spi electrical characteristic num 1 1 refer to figure a-7 through figure a-10 . c rating 2 2 all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. all timing assumes slew rate control disabled and high drive strength enabled for spi output pins. symbol min max unit 1d cycle time master slave t sck t sck 2 4 2048 t cyc t cyc 2d enable lead time master slave t lead t lead 1/2 1/2 t sck t sck 3d enable lag time master slave t lag t lag 1/2 1/2 t sck t sck 4d clock (spsck) high time master and slave t sckh (1/2 t sck )?25 ns 5d clock (spsck) low time master and slave t sckl (1/2 t sck ) ?25 ns 6d data setup time (inputs) master slave t si(m) t si(s) 30 30 ns ns 7d data hold time (inputs) master slave t hi(m) t hi(s) 30 30 ns ns 8d access time, slave 3 3 time to data active from high-impedance state. t a 04 0n s 9d disable time, slave 4 4 hold time to high-impedance state. t dis ? 0n s 10 d data setup time (outputs) master slave t so t so 25 25 ns ns 11 d data hold time (outputs) master slave t ho t ho ?0 ?0 ns ns 12 d operating frequency 5 master slave 5 maximum baud rate must be limited to 5 mhz due to pad input characteristics. f op f op f bus /2048 dc 5 f bus /4 mhz
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 388 freescale semiconductor figure a-7. spi master timing (cpha = 0) figure a-8. spi master timing (cpha = 1) sck (output) sck (output) miso (input) mosi (output) ss 1 (output) msb in 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (modfen = 1, ssoe = 1). 1 2 3 5 6 7 10 11 5 10 4 4 sck (output) sck (output) miso (input) mosi (output) msb in (2) bit 6 . . . 1 lsb in msb out (2) lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) ss (1) (output) 1. ss output mode (modfen = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 3 4 5 6 7 10 11 5 4
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 389 figure a-9. spi slave timing (cpha = 0) figure a-10. spi slave timing (cpha = 1) sck (input) sck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1. not defined but normally msb of character just received 1 2 3 4 6 7 8 9 10 11 5 5 4 sck (input) sck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1. not defined but normally lsb of character just received 1 2 3 4 6 7 8 9 10 11 4 5 5
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 390 freescale semiconductor a.13 flash and eeprom this section provides details about program/erase times and program-erase endurance for the flash and eeprom memory. program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see chapter 4, ?emory . table a-17. flash and eeprom characteristics num c rating symbol min typical max unit 1 supply voltage for program/erase v prog/erase 2.7 5.5 v 2 supply voltage for read operation 0 < f bus < 8 mhz 0 appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 freescale semiconductor 391 a.14 emc performance electromagnetic compatibility (emc) performance is highly dependant on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation all play a signi?ant role in emc performance. the system designer should consult freescale applications notes such as an2321, an1050, an1263, an2764, and an1259 for advice and guidance speci?ally targeted at optimizing emc performance. a.14.1 radiated emissions microcontroller radiated rf emissions are measured from 150 khz to 1 ghz using the tem/gtem cell method in accordance with the iec 61967-2 and sae j1752/3 standards. the measurement is performed with the microcontroller installed on a custom emc evaluation board while running specialized emc test software. the radiated emissions from the microcontroller are measured in a tem cell in two package orientations (north and east). for more detailed information concerning the evaluation results, conditions and setup, please refer to the emc evaluation report for this device. the maximum radiated rf emissions of the tested con?uration in all orientations are less than or equal to the reported emissions levels. table a-18. radiated emissions for 3m05c mask set parameter symbol conditions frequency f osc /f cpu level 1 (max) 1 data based on quali?ation test results. unit radiated emissions, electric ?ld ?conditions - v re_tem v dd =5 t a = +25 o c 64 lqfp 0.15 ?50 mhz 16 mhz crystal 20 mhz bus 18 dbv 50 ?150 mhz 18 150 ?500 mhz 13 500 ?1000 mhz 7 iec level l sae level 2
appendix a electrical characteristics mc9s08de60 series data sheet, rev. 3 392 freescale semiconductor
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 393 appendix b timer pulse-width modulator (tpmv2) note this chapter refers to s08tpm version 2, which applies to the 3m05c and older mask sets of this device. )m74k and newer mask set devices use s08tpm version 3. if your device uses mask 0m74k or newer, please refer to chapter 16, ?imer pulse-width modulator (s08tpmv3) for information pertaining to that module. the tpm uses one input/output (i/o) pin per channel, tpmxchn where x is the tpm number (for example, 1 or 2) and n is the channel number (for example, 0?). the tpm shares its i/o pins with general-purpose i/o port pins (refer to the pins and connections chapter for more information). b.0.1 features the tpm has the following features: each tpm may be con?ured for buffered, center-aligned pulse-width modulation (cpwm) on all channels clock sources independently selectable per tpm (multiple tpms device) selectable clock sources (device dependent): bus clock, ?ed system clock, external pin clock prescaler taps for divide by 1, 2, 4, 8, 16, 32, 64, or 128 16-bit free-running or up/down (cpwm) count operation 16-bit modulus register to control counter range timer system enable one interrupt per channel plus a terminal count interrupt for each tpm module (multiple tpms device) channel features: each channel may be input capture, output compare, or buffered edge-aligned pwm rising-edge, falling-edge, or any-edge input capture trigger set, clear, or toggle output compare action selectable polarity on pwm outputs b.0.2 block diagram figure b-1 shows the structure of a tpm. some mcus include more than one tpm, with various numbers of channels.
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 394 freescale semiconductor figure b-1. tpm block diagram the central component of the tpm is the 16-bit counter that can operate as a free-running counter, a modulo counter, or an up-/down-counter when the tpm is con?ured for center-aligned pwm. the tpm counter (when operating in normal up-counting mode) provides the timing reference for the input capture, output compare, and edge-aligned pwm functions. the timer counter modulo registers, tpmxmodh:tpmxmodl, control the modulo value of the counter. (the values 0x0000 or 0xffff effectively make the counter free running.) software can read the counter value at any time without affecting the counting sequence. any write to either byte of the tpmxcnt counter resets the counter regardless of the data value written. prescale and select 16-bit comparator main 16-bit counter 16-bit comparator 16-bit latch port 16-bit comparator 16-bit latch channel 0 channel 1 internal bus logic interrupt port logic 16-bit comparator 16-bit latch channel n port logic counter reset divide by clock source off, bus, xclk, ext busclk xclk select sync interrupt interrupt interrupt 1, 2, 4, 8, 16, 32, 64, or 128 logic logic logic logic clksa clksb ps2 ps1 ps0 cpwms toie tof els0a ch0f els0b els1b els1a elsnb elsna ch1f chnf ch0ie ch1ie chnie ms1b ms0b msnb ms0a ms1a msna . . . . . . . . . tpmxmodh:tpmxmodl tpmxc0vh:tpmxc0vl tpmxc1vh:tpmxc1vl tpmxcnvh:tpmxcnvl tpmxchn tpmxch1 tpmxch0 tpmxclk
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 395 all tpm channels are programmable independently as input capture, output compare, or buffered edge-aligned pwm channels. b.1 external signal description when any pin associated with the timer is con?ured as a timer input, a passive pullup can be enabled. after reset, the tpm modules are disabled and all pins default to general-purpose inputs with the passive pullups disabled. b.1.1 external tpm clock sources when control bits clksb:clksa in the timer status and control register are set to 1:1, the prescaler and consequently the 16-bit counter for tpmx are driven by an external clock source, tpmxclk, connected to an i/o pin. a synchronizer is needed between the external clock and the rest of the tpm. this synchronizer is clocked by the bus clock so the frequency of the external source must be less than one-half the frequency of the bus rate clock. the upper frequency limit for this external clock source is speci?d to be one-fourth the bus frequency to conservatively accommodate duty cycle and phase-locked loop (pll) or frequency-locked loop (fll) frequency jitter effects. on some devices the external clock input is shared with one of the tpm channels. when a tpm channel is shared as the external clock input, the associated tpm channel cannot use the pin. (the channel can still be used in output compare mode as a software timer.) also, if one of the tpm channels is used as the external clock input, the corresponding elsnb:elsna control bits must be set to 0:0 so the channel is not trying to use the same pin. b.1.2 tpmxchn ?tpmx channel n i/o pins each tpm channel is associated with an i/o pin on the mcu. the function of this pin depends on the con?uration of the channel. in some cases, no pin function is needed so the pin reverts to being controlled by general-purpose i/o controls. when a timer has control of a port pin, the port data and data direction registers do not affect the related pin(s). see the pins and connections chapter for additional information about shared pin functions. b.2 register de?ition the tpm includes: an 8-bit status and control register (tpmxsc) a 16-bit counter (tpmxcnth:tpmxcntl) a 16-bit modulo register (tpmxmodh:tpmxmodl) each timer channel has: an 8-bit status and control register (tpmxcnsc) a 16-bit channel value register (tpmxcnvh:tpmxcnvl) refer to the direct-page register summary in the memory chapter of this data sheet for the absolute address assignments for all tpm registers. this section refers to registers and control bits only by their names. a
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 396 freescale semiconductor freescale-provided equate or header ?e is used to translate these names into the appropriate absolute addresses. b.2.1 timer status and control register (tpmxsc) tpmxsc contains the over?w status ?g and control bits that are used to con?ure the interrupt enable, tpm con?uration, clock source, and prescale divisor. these controls relate to all channels within this timer module. 76543210 rtof toie cpwms clksb clksa ps2 ps1 ps0 w reset 00000000 = unimplemented or reserved figure b-2. timer status and control register (tpmxsc) table b-1. tpmxsc register field descriptions field description 7 tof timer over?w flag ?this ?g is set when the tpm counter changes to 0x0000 after reaching the modulo value programmed in the tpm counter modulo registers. when the tpm is con?ured for cpwm, tof is set after the counter has reached the value in the modulo register, at the transition to the next lower count value. clear tof by reading the tpm status and control register when tof is set and then writing a 0 to tof. if another tpm over?w occurs before the clearing sequence is complete, the sequence is reset so tof would remain set after the clear sequence was completed for the earlier tof. reset clears tof. writing a 1 to tof has no effect. 0 tpm counter has not reached modulo value or over?w 1 tpm counter has over?wed 6 toie timer over?w interrupt enable ?this read/write bit enables tpm over?w interrupts. if toie is set, an interrupt is generated when tof equals 1. reset clears toie. 0 tof interrupts inhibited (use software polling) 1 tof interrupts enabled 5 cpwms center-aligned pwm select this read/write bit selects cpwm operating mode. reset clears this bit so the tpm operates in up-counting mode for input capture, output compare, and edge-aligned pwm functions. setting cpwms recon?ures the tpm to operate in up-/down-counting mode for cpwm functions. reset clears cpwms. 0 all tpmx channels operate as input capture, output compare, or edge-aligned pwm mode as selected by the msnb:msna control bits in each channels status and control register 1 all tpmx channels operate in center-aligned pwm mode 4:3 clks[b:a] clock source select as shown in table b-2 , this 2-bit ?ld is used to disable the tpm system or select one of three clock sources to drive the counter prescaler. the external source and the xclk are synchronized to the bus clock by an on-chip synchronization circuit. 2:0 ps[2:0] prescale divisor select ?this 3-bit ?ld selects one of eight divisors for the tpm clock input as shown in table b-3 . this prescaler is located after any clock source synchronization or clock source selection, so it affects whatever clock source is selected to drive the tpm system.
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 397 b.2.2 timer counter registers (tpmxcnth:tpmxcntl) the two read-only tpm counter registers contain the high and low bytes of the value in the tpm counter. reading either byte (tpmxcnth or tpmxcntl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. this allows coherent 16-bit reads in either order. the coherency mechanism is automatically restarted by an mcu reset, a write of any value to tpmxcnth or tpmxcntl, or any write to the timer status/control register (tpmxsc). reset clears the tpm counter registers. table b-2. tpm clock source selection clksb:clksa tpm clock source to prescaler input 0:0 no clock selected (tpmx disabled) 0:1 bus rate clock (busclk) 1:0 fixed system clock (xclk) 1:1 external source (tpmxclk) 1,2 1 the maximum frequency that is allowed as an external clock is one-fourth of the bus frequency. 2 if the external clock input is shared with channel n and is selected as the tpm clock source, the corresponding elsnb:elsna control bits should be set to 0:0 so channel n does not try to use the same pin for a con?cting function. table b-3. prescale divisor selection ps2:ps1:ps0 tpm clock source divided-by 0:0:0 1 0:0:1 2 0:1:0 4 0:1:1 8 1:0:0 16 1:0:1 32 1:1:0 64 1:1:1 128 76543210 r bit 15 14 13 12 11 10 9 bit 8 w any write to tpmxcnth clears the 16-bit counter. reset 00000000 figure b-3. timer counter register high (tpmxcnth)
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 398 freescale semiconductor when background mode is active, the timer counter and the coherency mechanism are frozen such that the buffer latches remain in the state they were in when the background mode became active even if one or both bytes of the counter are read while background mode is active. b.2.3 timer counter modulo registers (tpmxmodh:tpmxmodl) the read/write tpm modulo registers contain the modulo value for the tpm counter. after the tpm counter reaches the modulo value, the tpm counter resumes counting from 0x0000 at the next clock (cpwms = 0) or starts counting down (cpwms = 1), and the over?w ?g (tof) becomes set. writing to tpmxmodh or tpmxmodl inhibits tof and over?w interrupts until the other byte is written. reset sets the tpm counter modulo registers to 0x0000, which results in a free-running timer counter (modulo disabled). it is good practice to wait for an over?w interrupt so both bytes of the modulo register can be written well before a new over?w. an alternative approach is to reset the tpm counter before writing to the tpm modulo registers to avoid confusion about when the ?st counter over?w will occur. 76543210 r bit 7 654321 bit 0 w any write to tpmxcntl clears the 16-bit counter. reset 00000000 figure b-4. timer counter register low (tpmxcntl) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure b-5. timer counter modulo register high (tpmxmodh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure b-6. timer counter modulo register low (tpmxmodl)
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 399 b.2.4 timer channel n status and control register (tpmxcnsc) tpmxcnsc contains the channel interrupt status ?g and control bits that are used to con?ure the interrupt enable, channel con?uration, and pin function. 76543210 r chnf chnie msnb msna elsnb elsna 00 w reset 00000000 = unimplemented or reserved figure b-7. timer channel n status and control register (tpmxcnsc) table b-4. tpmxcnsc register field descriptions field description 7 chnf channel n flag when channel n is con?ured for input capture, this ?g bit is set when an active edge occurs on the channel n pin. when channel n is an output compare or edge-aligned pwm channel, chnf is set when the value in the tpm counter registers matches the value in the tpm channel n value registers. this ?g is seldom used with center-aligned pwms because it is set every time the counter matches the channel value register, which correspond to both edges of the active duty cycle period. a corresponding interrupt is requested when chnf is set and interrupts are enabled (chnie = 1). clear chnf by reading tpmxcnsc while chnf is set and then writing a 0 to chnf. if another interrupt request occurs before the clearing sequence is complete, the sequence is reset so chnf would remain set after the clear sequence was completed for the earlier chnf. this is done so a chnf interrupt request cannot be lost by clearing a previous chnf. reset clears chnf. writing a 1 to chnf has no effect. 0 no input capture or output compare event occurred on channel n 1 input capture or output compare event occurred on channel n 6 chnie channel n interrupt enable ?this read/write bit enables interrupts from channel n. reset clears chnie. 0 channel n interrupt requests disabled (use software polling) 1 channel n interrupt requests enabled 5 msnb mode select b for tpm channel n ?when cpwms = 0, msnb = 1 con?ures tpm channel n for edge-aligned pwm mode. for a summary of channel mode and setup controls, refer to table b-5 . 4 msna mode select a for tpm channel n when cpwms = 0 and msnb = 0, msna con?ures tpm channel n for input capture mode or output compare mode. refer to table b-5 for a summary of channel mode and setup controls. 3:2 elsn[b:a] edge/level select bits ?depending on the operating mode for the timer channel as set by cpwms:msnb:msna and shown in table b-5 , these bits select the polarity of the input edge that triggers an input capture event, select the level that will be driven in response to an output compare match, or select the polarity of the pwm output. setting elsnb:elsna to 0:0 con?ures the related timer pin as a general-purpose i/o pin unrelated to any timer channel functions. this function is typically used to temporarily disable an input capture channel or to make the timer pin available as a general-purpose i/o pin when the associated timer channel is set up as a software timer that does not require the use of a pin.
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 400 freescale semiconductor if the associated port pin is not stable for at least two bus clock cycles before changing to input capture mode, it is possible to get an unexpected indication of an edge trigger. typically, a program would clear status ?gs after changing channel con?uration bits and before enabling channel interrupts or using the status ?gs to avoid any unexpected behavior. b.2.5 timer channel value registers (tpmxcnvh:tpmxcnvl) these read/write registers contain the captured tpm counter value of the input capture function or the output compare value for the output compare or pwm functions. the channel value registers are cleared by reset. table b-5. mode, edge, and level selection cpwms msnb:msna elsnb:elsna mode con?uration x xx 00 pin not used for tpm channel; use as an external clock for the tpm or revert to general-purpose i/o 0 00 01 input capture capture on rising edge only 10 capture on falling edge only 11 capture on rising or falling edge 01 00 output compare software compare only 01 toggle output on compare 10 clear output on compare 11 set output on compare 1x 10 edge-aligned pwm high-true pulses (clear output on compare) x1 low-true pulses (set output on compare) 1 xx 10 center-aligned pwm high-true pulses (clear output on compare-up) x1 low-true pulses (set output on compare-up) 76543210 r bit 15 14 13 12 11 10 9 bit 8 w reset 00000000 figure b-8. timer channel value register high (tpmxcnvh) 76543210 r bit 7 654321 bit 0 w reset 00000000 figure b-9. timer channel value register low (tpmxcnvl)
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 401 in input capture mode, reading either byte (tpmxcnvh or tpmxcnvl) latches the contents of both bytes into a buffer where they remain latched until the other byte is read. this latching mechanism also resets (becomes unlatched) when the tpmxcnsc register is written. in output compare or pwm modes, writing to either byte (tpmxcnvh or tpmxcnvl) latches the value into a buffer. when both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. this latching mechanism may be manually reset by writing to the tpmxcnsc register. this latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. b.3 functional description all tpm functions are associated with a main 16-bit counter that allows ?xible selection of the clock source and prescale divisor. a 16-bit modulo register also is associated with the main 16-bit counter in the tpm. each tpm channel is optionally associated with an mcu pin and a maskable interrupt function. the tpm has center-aligned pwm capabilities controlled by the cpwms control bit in tpmxsc. when cpwms is set to 1, timer counter tpmxcnt changes to an up-/down-counter and all channels in the associated tpm act as center-aligned pwm channels. when cpwms = 0, each channel can independently be con?ured to operate in input capture, output compare, or buffered edge-aligned pwm mode. the following sections describe the main 16-bit counter and each of the timer operating modes (input capture, output compare, edge-aligned pwm, and center-aligned pwm). because details of pin operation and interrupt activity depend on the operating mode, these topics are covered in the associated mode sections. b.3.1 counter all timer functions are based on the main 16-bit counter (tpmxcnth:tpmxcntl). this section discusses selection of the clock source, up-counting vs. up-/down-counting, end-of-count over?w, and manual counter reset. after any mcu reset, clksb:clksa = 0:0 so no clock source is selected and the tpm is inactive. normally, clksb:clksa would be set to 0:1 so the bus clock drives the timer counter. the clock source for the tpm can be selected to be off, the bus clock (busclk), the ?ed system clock (xclk), or an external input. the maximum frequency allowed for the external clock option is one-fourth the bus rate. refer to section b.2.1, ?imer status and control register (tpmxsc) and table b-2 for more information about clock source selection. when the microcontroller is in active background mode, the tpm temporarily suspends all counting until the microcontroller returns to normal user operating mode. during stop mode, all tpm clocks are stopped; therefore, the tpm is effectively disabled until clocks resume. during wait mode, the tpm continues to operate normally. the main 16-bit counter has two counting modes. when center-aligned pwm is selected (cpwms = 1), the counter operates in up-/down-counting mode. otherwise, the counter operates as a simple up-counter.
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 402 freescale semiconductor as an up-counter, the main 16-bit counter counts from 0x0000 through its terminal count and then continues with 0x0000. the terminal count is 0xffff or a modulus value in tpmxmodh:tpmxmodl. when center-aligned pwm operation is speci?d, the counter counts upward from 0x0000 through its terminal count and then counts downward to 0x0000 where it returns to up-counting. both 0x0000 and the terminal count value (value in tpmxmodh:tpmxmodl) are normal length counts (one timer clock period long). an interrupt ?g and enable are associated with the main 16-bit counter. the timer over?w ?g (tof) is a software-accessible indication that the timer counter has over?wed. the enable signal selects between software polling (toie = 0) where no hardware interrupt is generated, or interrupt-driven operation (toie = 1) where a static hardware interrupt is automatically generated whenever the tof ?g is 1. the conditions that cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the main 16-bit counter counts from 0x0000 through 0xffff and over?ws to 0x0000 on the next counting clock. tof becomes set at the transition from 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the main 16-bit counter is operating in up-/down-counting mode, the tof ?g gets set as the counter changes direction at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the 0x0000 count value corresponds to the center of a period.) because the hcs08 mcu is an 8-bit architecture, a coherency mechanism is built into the timer counter for read operations. whenever either byte of the counter is read (tpmxcnth or tpmxcntl), both bytes are captured into a buffer so when the other byte is read, the value will represent the other byte of the count at the time the ?st byte was read. the counter continues to count normally, but no new value can be read from either byte until both bytes of the old count have been read. the main timer counter can be reset manually at any time by writing any value to either byte of the timer count tpmxcnth or tpmxcntl. resetting the counter in this manner also resets the coherency mechanism in case only one byte of the counter was read before resetting the count. b.3.2 channel mode selection provided cpwms = 0 (center-aligned pwm operation is not speci?d), the msnb and msna control bits in the channel n status and control registers determine the basic mode of operation for the corresponding channel. choices include input capture, output compare, and buffered edge-aligned pwm. b.3.2.1 input capture mode with the input capture function, the tpm can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tpm latches the contents of the tpm counter into the channel value registers (tpmxcnvh:tpmxcnvl). rising edges, falling edges, or any edge may be chosen as the active edge that triggers an input capture. when either byte of the 16-bit capture register is read, both bytes are latched into a buffer to support coherent 16-bit accesses regardless of order. the coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc).
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 403 an input capture event sets a ?g bit (chnf) that can optionally generate a cpu interrupt request. b.3.2.2 output compare mode with the output compare function, the tpm can generate timed pulses with programmable position, polarity, duration, and frequency. when the counter reaches the value in the channel value registers of an output compare channel, the tpm can set, clear, or toggle the channel pin. in output compare mode, values are transferred to the corresponding timer channel value registers only after both 8-bit bytes of a 16-bit register have been written. this coherency sequence can be manually reset by writing to the channel status/control register (tpmxcnsc). an output compare event sets a ?g bit (chnf) that can optionally generate a cpu interrupt request. b.3.2.3 edge-aligned pwm mode this type of pwm output uses the normal up-counting mode of the timer counter (cpwms = 0) and can be used when other channels in the same tpm are con?ured for input capture or output compare functions. the period of this pwm signal is determined by the setting in the modulus register (tpmxmodh:tpmxmodl). the duty cycle is determined by the setting in the timer channel value register (tpmxcnvh:tpmxcnvl). the polarity of this pwm signal is determined by the setting in the elsna control bit. duty cycle cases of 0 percent and 100 percent are possible. as figure b-10 shows, the output compare value in the tpm channel registers determines the pulse width (duty cycle) of the pwm signal. the time between the modulus over?w and the output compare is the pulse width. if elsna = 0, the counter over?w forces the pwm signal high and the output compare forces the pwm signal low. if elsna = 1, the counter over?w forces the pwm signal low and the output compare forces the pwm signal high. figure b-10. pwm period and pulse width (elsna = 0) when the channel value register is set to 0x0000, the duty cycle is 0 percent. by setting the timer channel value register (tpmxcnvh:tpmxcnvl) to a value greater than the modulus setting, 100% duty cycle can be achieved. this implies that the modulus setting must be less than 0xffff to get 100% duty cycle. because the hcs08 is a family of 8-bit mcus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to either register, tpmxcnvh or tpmxcnvl, write to buffer registers. in edge-pwm mode, values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and period pulse width overflow overflow overflow output compare output compare output compare tpmxc
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 404 freescale semiconductor the value in the tpmxcnth:tpmxcntl counter is 0x0000. (the new duty cycle does not take effect until the next full period.) b.3.3 center-aligned pwm mode this type of pwm output uses the up-/down-counting mode of the timer counter (cpwms = 1). the output compare value in tpmxcnvh:tpmxcnvl determines the pulse width (duty cycle) of the pwm signal and the period is determined by the value in tpmxmodh:tpmxmodl. tpmxmodh:tpmxmodl should be kept in the range of 0x0001 to 0x7fff because values outside this range can produce ambiguous results. elsna will determine the polarity of the cpwm output. pulse width = 2 x (tpmxcnvh:tpmxcnvl) eqn. 17-1 period = 2 x (tpmxmodh:tpmxmodl); for tpmxmodh:tpmxmodl = 0x0001?x7fff eqn. 17-2 if the channel value register tpmxcnvh:tpmxcnvl is zero or negative (bit 15 set), the duty cycle will be 0%. if tpmxcnvh:tpmxcnvl is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100% because the duty cycle compare will never occur. this implies the usable range of periods set by the modulus register is 0x0001 through 0x7ffe (0x7fff if generation of 100% duty cycle is not necessary). this is not a signi?ant limitation because the resulting period is much longer than required for normal applications. tpmxmodh:tpmxmodl = 0x0000 is a special case that should not be used with center-aligned pwm mode. when cpwms = 0, this case corresponds to the counter running free from 0x0000 through 0xffff, but when cpwms = 1 the counter needs a valid match to the modulus register somewhere other than at 0x0000 in order to change directions from up-counting to down-counting. figure b-11 shows the output compare value in the tpm channel registers (multiplied by 2), which determines the pulse width (duty cycle) of the cpwm signal. if elsna = 0, the compare match while counting up forces the cpwm output signal low and a compare match while counting down forces the output high. the counter counts up until it reaches the modulo setting in tpmxmodh:tpmxmodl, then counts down until it reaches zero. this sets the period equal to two times tpmxmodh:tpmxmodl. figure b-11. cpwm period and pulse width (elsna = 0) center-aligned pwm outputs typically produce less noise than edge-aligned pwms because fewer i/o pin transitions are lined up at the same system clock edge. this type of pwm is also required for some types of motor drives. period pulse width count = count = 0 output compare (count up) output compare (count down) count = tpmxmodh:tpmx tpm1c tpmxmodh:tpmx 2 x 2 x
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 freescale semiconductor 405 because the hcs08 is a family of 8-bit mcus, the settings in the timer channel registers are buffered to ensure coherent 16-bit updates and to avoid unexpected pwm pulse widths. writes to any of the registers, tpmxmodh, tpmxmodl, tpmxcnvh, and tpmxcnvl, actually write to buffer registers. values are transferred to the corresponding timer channel registers only after both 8-bit bytes of a 16-bit register have been written and the timer counter over?ws (reverses direction from up-counting to down-counting at the end of the terminal count in the modulus register). this tpmxcnt over?w requirement only applies to pwm channels, not output compares. optionally, when tpmxcnth:tpmxcntl = tpmxmodh:tpmxmodl, the tpm can generate a tof interrupt at the end of this count. the user can choose to reload any number of the pwm buffers, and they will all update simultaneously at the start of a new period. writing to tpmxsc cancels any values written to tpmxmodh and/or tpmxmodl and resets the coherency mechanism for the modulo registers. writing to tpmxcnsc cancels any values written to the channel value registers and resets the coherency mechanism for tpmxcnvh:tpmxcnvl. b.4 tpm interrupts the tpm generates an optional interrupt for the main counter over?w and an interrupt for each channel. the meaning of channel interrupts depends on the mode of operation for each channel. if the channel is con?ured for input capture, the interrupt ?g is set each time the selected input capture edge is recognized. if the channel is con?ured for output compare or pwm modes, the interrupt ?g is set each time the main timer counter matches the value in the 16-bit channel value register. see the resets, interrupts, and system con?uration chapter for absolute interrupt vector addresses, priority, and local interrupt mask control bits. for each interrupt source in the tpm, a ?g bit is set on recognition of the interrupt condition such as timer over?w, channel input capture, or output compare events. this ?g may be read (polled) by software to verify that the action has occurred, or an associated enable bit (toie or chnie) can be set to enable hardware interrupt generation. while the interrupt enable bit is set, a static interrupt will be generated whenever the associated interrupt ?g equals 1. it is the responsibility of user software to perform a sequence of steps to clear the interrupt ?g before returning from the interrupt service routine. b.4.1 clearing timer interrupt flags tpm interrupt ?gs are cleared by a 2-step process that includes a read of the ?g bit while it is set (1) followed by a write of 0 to the bit. if a new event is detected between these two steps, the sequence is reset and the interrupt ?g remains set after the second step to avoid the possibility of missing the new event. b.4.2 timer over?w interrupt description the conditions that cause tof to become set depend on the counting mode (up or up/down). in up-counting mode, the 16-bit timer counter counts from 0x0000 through 0xffff and over?ws to 0x0000 on the next counting clock. tof becomes set at the transition from 0xffff to 0x0000. when a modulus limit is set, tof becomes set at the transition from the value set in the modulus register to 0x0000. when the counter is operating in up-/down-counting mode, the tof ?g gets set as the counter changes direction
appendix b timer pulse-width modulator (tpmv2) mc9s08de60 series data sheet, rev. 3 406 freescale semiconductor at the transition from the value set in the modulus register and the next lower count value. this corresponds to the end of a pwm period. (the 0x0000 count value corresponds to the center of a period.) b.4.3 channel event interrupt description the meaning of channel interrupts depends on the current mode of the channel (input capture, output compare, edge-aligned pwm, or center-aligned pwm). when a channel is con?ured as an input capture channel, the elsnb:elsna control bits select rising edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. when the selected edge is detected, the interrupt ?g is set. the ?g is cleared by the 2-step sequence described in section b.4.1, ?learing timer interrupt flags . when a channel is con?ured as an output compare channel, the interrupt ?g is set each time the main timer counter matches the 16-bit value in the channel value register. the ?g is cleared by the 2-step sequence described in section b.4.1, ?learing timer interrupt flags . b.4.4 pwm end-of-duty-cycle events for channels that are con?ured for pwm operation, there are two possibilities: when the channel is con?ured for edge-aligned pwm, the channel ?g is set when the timer counter matches the channel value register that marks the end of the active duty cycle period. when the channel is con?ured for center-aligned pwm, the timer count matches the channel value register twice during each pwm cycle. in this cpwm case, the channel ?g is set at the start and at the end of the active duty cycle, which are the times when the timer counter matches the channel value register. the ?g is cleared by the 2-step sequence described in section b.4.1, ?learing timer interrupt flags .
mc9s08de60 series data sheet, rev. 3 freescale semiconductor 407 appendix c ordering information and mechanical drawings c.1 ordering information this section contains ordering information for mc9s08de60 series devices. example of the device numbering system: c.1.1 mc9s08de60 series devices c.2 mechanical drawings the following pages are mechanical drawings for the packages described in the following table: table c-1. devices in the mc9s08de60 series device number memory available packages 1 1 see table c-2 for package information. flash 2 2 flash sizes shown with ecc disabled. ram eeprom mc9s08de60 60,032 4096 2048 64-lqfp MC9S08DE32 33,792 2048 1024 table c-2. package descriptions pin count type abbreviation designator document no. 64 low quad flat package lqfp lh 98ass23234w mc temperature range family memory status core (c = ?0c to 85c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see table c-2 ) approximate flash de f1 (s = auto qualified) m (v = ?0 c to 105 c) (m = ?0c to 125c) size in kb 60 mast set identifier only appears for ?uto qualified?part numbers beginning with ? f1 = 1m74k mask set

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